mux16.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 612 行 · 第 1/5 页
RPT
612 行
Y2 | 8 149 | RESERVED
Y3 | 9 148 | RESERVED
RESERVED | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
b10 | 14 143 | RESERVED
a10 | 15 142 | RESERVED
RESERVED | 16 141 | Y15
MUL | 17 140 | a9
EQUAL | 18 139 | a8
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | a11
VCCIO | 22 135 | Y6
GND | 23 134 | RESERVED
RESERVED | 24 133 | RESERVED
RESERVED | 25 132 | RESERVED
RESERVED | 26 131 | RESERVED
RESERVED | 27 EP1K100QC208-3 130 | VCCINT
RESERVED | 28 129 | GND
RESERVED | 29 128 | RESERVED
RESERVED | 30 127 | RESERVED
RESERVED | 31 126 | RESERVED
GND | 32 125 | RESERVED
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | RESERVED
RESERVED | 37 120 | RESERVED
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
Y1 | 41 116 | RESERVED
VCCIO | 42 115 | RESERVED
GND | 43 114 | b15
Y4 | 44 113 | a15
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | RESERVED
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
R R R b a R G R R R R b R V R R b R Y V R R a G V a a b G G b V R a R R R R V Y R b R b R V Y Y Y Y b R
E E E 3 7 E N E E E E 1 E C E E 8 E 5 C E E 4 N C 0 2 2 N N 1 C E 1 E E E E C 1 E 6 E 1 E C 8 7 1 1 7 E
S S S S D S S S S S C S S S C S S D C D D 2 C S 3 S S S S C 0 S S 1 S C 2 3 S
E E E E E E E E E I E E E I E E I I E E E E E I E E E I E
R R R R R R R R R O R R R N R R N O R R R R R N R R R O R
V V V V V V V V V V V V T V V T V V V V V T V V V V
E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\cal\mux16.rpt
mux16
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A27 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 8/26( 30%)
C1 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 4/26( 15%)
C2 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/26( 34%)
C4 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 9/26( 34%)
C5 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/26( 26%)
C6 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 16/26( 61%)
C8 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/26( 42%)
C9 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 10/26( 38%)
C11 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 9/26( 34%)
C12 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 9/26( 34%)
C14 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 11/26( 42%)
C16 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/26( 53%)
C19 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 8/26( 30%)
C20 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 11/26( 42%)
C21 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/26( 15%)
C22 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
C23 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
C24 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 12/26( 46%)
C26 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 9/26( 34%)
C28 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/26( 42%)
C30 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 15/26( 57%)
C31 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 12/26( 46%)
C33 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 12/26( 46%)
C34 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
C36 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/26( 38%)
C39 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/26( 38%)
C40 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/26( 26%)
C44 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
C46 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 7/26( 26%)
C47 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/26( 42%)
C50 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 17/26( 65%)
C52 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
D9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/26( 7%)
K1 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 6/26( 23%)
K5 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 11/26( 42%)
K9 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 10/26( 38%)
K13 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 2/26( 7%)
K16 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/26( 11%)
K17 7/ 8( 87%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 6/26( 23%)
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