b16jianfa.vhd

来自「ProtelDXp 实现计算器功能」· VHDL 代码 · 共 31 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY B16JIANFA IS
PORT
(
	DEC,EQUAL	:IN STD_LOGIC;
	N1,N2		:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	CO			:OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
	S			:OUT STD_LOGIC);
END;
ARCHITECTURE A OF B16JIANFA IS
SIGNAL SIN	:STD_LOGIC_VECTOR(16 DOWNTO 0);
BEGIN
	PROCESS(DEC,EQUAL)
BEGIN	
		SIN<=N1+(NOT('0'&N2)+1);	
IF DEC='1'AND EQUAL='1'THEN
	IF SIN(16)='1'THEN
		CO<=NOT(SIN)+1;
		S<='1';
	ELSE
		CO<=SIN(15 DOWNTO 0);
		S<='0';
	END IF;
END IF;	
END PROCESS;
END;