b16jiafa.rpt

来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,020 行 · 第 1/4 页

  _EQ024 =  _LC2_D36 &  N110 &  N210
         #  _LC2_D36 & !N110 & !N210
         # !_LC2_D36 & !N110 &  N210
         # !_LC2_D36 &  N110 & !N210;

-- Node name is '|LPM_ADD_SUB:139|addcore:adder|:188' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC5_B4', type is buried 
_LC5_B4  = LCELL( _EQ025);
  _EQ025 =  _LC4_B4 &  N111 &  N211
         #  _LC4_B4 & !N111 & !N211
         # !_LC4_B4 & !N111 &  N211
         # !_LC4_B4 &  N111 & !N211;

-- Node name is '|LPM_ADD_SUB:139|addcore:adder|:189' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_B4', type is buried 
_LC8_B4  = LCELL( _EQ026);
  _EQ026 =  _LC7_B4 &  N112 &  N212
         #  _LC7_B4 & !N112 & !N212
         # !_LC7_B4 & !N112 &  N212
         # !_LC7_B4 &  N112 & !N212;

-- Node name is '|LPM_ADD_SUB:139|addcore:adder|:190' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC2_K13', type is buried 
_LC2_K13 = LCELL( _EQ027);
  _EQ027 =  _LC3_B4 &  N113 &  N213
         #  _LC3_B4 & !N113 & !N213
         # !_LC3_B4 & !N113 &  N213
         # !_LC3_B4 &  N113 & !N213;

-- Node name is '|LPM_ADD_SUB:139|addcore:adder|:191' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC4_K13', type is buried 
_LC4_K13 = LCELL( _EQ028);
  _EQ028 =  _LC3_K13 &  N114 &  N214
         #  _LC3_K13 & !N114 & !N214
         # !_LC3_K13 & !N114 &  N214
         # !_LC3_K13 &  N114 & !N214;

-- Node name is '|LPM_ADD_SUB:139|addcore:adder|:192' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC8_K13', type is buried 
_LC8_K13 = LCELL( _EQ029);
  _EQ029 =  _LC7_K13 &  N115 &  N215
         #  _LC7_K13 & !N115 & !N215
         # !_LC7_K13 & !N115 &  N215
         # !_LC7_K13 &  N115 & !N215;

-- Node name is ':58' 
-- Equation name is '_LC4_F42', type is buried 
_LC4_F42 = LCELL( _EQ030);
  _EQ030 =  ADD &  EQUAL;

-- Node name is ':181' 
-- Equation name is '_LC1_K13', type is buried 
_LC1_K13 = LCELL( _EQ031);
  _EQ031 = !ADD &  _LC1_K13
         # !EQUAL &  _LC1_K13
         #  ADD &  EQUAL &  _LC8_K13;

-- Node name is ':187' 
-- Equation name is '_LC5_K13', type is buried 
_LC5_K13 = LCELL( _EQ032);
  _EQ032 = !ADD &  _LC5_K13
         # !EQUAL &  _LC5_K13
         #  ADD &  EQUAL &  _LC4_K13;

-- Node name is ':193' 
-- Equation name is '_LC6_K13', type is buried 
_LC6_K13 = LCELL( _EQ033);
  _EQ033 = !ADD &  _LC6_K13
         # !EQUAL &  _LC6_K13
         #  ADD &  EQUAL &  _LC2_K13;

-- Node name is ':199' 
-- Equation name is '_LC6_B4', type is buried 
_LC6_B4  = LCELL( _EQ034);
  _EQ034 = !ADD &  _LC6_B4
         # !EQUAL &  _LC6_B4
         #  ADD &  EQUAL &  _LC8_B4;

-- Node name is ':205' 
-- Equation name is '_LC1_B4', type is buried 
_LC1_B4  = LCELL( _EQ035);
  _EQ035 = !ADD &  _LC1_B4
         # !EQUAL &  _LC1_B4
         #  ADD &  EQUAL &  _LC5_B4;

-- Node name is ':211' 
-- Equation name is '_LC2_F42', type is buried 
_LC2_F42 = LCELL( _EQ036);
  _EQ036 = !ADD &  _LC2_F42
         # !EQUAL &  _LC2_F42
         #  ADD &  EQUAL &  _LC2_B4;

-- Node name is ':217' 
-- Equation name is '_LC6_D36', type is buried 
_LC6_D36 = LCELL( _EQ037);
  _EQ037 = !ADD &  _LC6_D36
         # !EQUAL &  _LC6_D36
         #  ADD &  EQUAL &  _LC8_D36;

-- Node name is ':223' 
-- Equation name is '_LC3_D36', type is buried 
_LC3_D36 = LCELL( _EQ038);
  _EQ038 = !ADD &  _LC3_D36
         # !EQUAL &  _LC3_D36
         #  ADD &  EQUAL &  _LC5_D36;

-- Node name is ':229' 
-- Equation name is '_LC3_D37', type is buried 
_LC3_D37 = LCELL( _EQ039);
  _EQ039 = !ADD &  _LC3_D37
         # !EQUAL &  _LC3_D37
         #  ADD &  EQUAL &  _LC1_D36;

-- Node name is ':235' 
-- Equation name is '_LC5_D52', type is buried 
_LC5_D52 = LCELL( _EQ040);
  _EQ040 = !ADD &  _LC5_D52
         # !EQUAL &  _LC5_D52
         #  ADD &  EQUAL &  _LC4_D52;

-- Node name is ':241' 
-- Equation name is '_LC6_D52', type is buried 
_LC6_D52 = LCELL( _EQ041);
  _EQ041 = !ADD &  _LC6_D52
         # !EQUAL &  _LC6_D52
         #  ADD &  EQUAL &  _LC2_D52;

-- Node name is ':247' 
-- Equation name is '_LC2_D37', type is buried 
_LC2_D37 = LCELL( _EQ042);
  _EQ042 = !ADD &  _LC2_D37
         # !EQUAL &  _LC2_D37
         #  ADD &  EQUAL &  _LC7_D37;

-- Node name is ':253' 
-- Equation name is '_LC8_D37', type is buried 
_LC8_D37 = LCELL( _EQ043);
  _EQ043 = !ADD &  _LC8_D37
         # !EQUAL &  _LC8_D37
         #  ADD &  EQUAL &  _LC5_D37;

-- Node name is ':259' 
-- Equation name is '_LC4_D37', type is buried 
_LC4_D37 = LCELL( _EQ044);
  _EQ044 = !ADD &  _LC4_D37
         # !EQUAL &  _LC4_D37
         #  ADD &  EQUAL &  _LC1_F42;

-- Node name is ':265' 
-- Equation name is '_LC6_F42', type is buried 
_LC6_F42 = LCELL( _EQ045);
  _EQ045 = !_LC4_F42 &  _LC6_F42
         #  _LC4_F42 & !_LC5_F42 &  N11
         #  _LC4_F42 &  _LC5_F42 & !N11;

-- Node name is ':271' 
-- Equation name is '_LC8_F42', type is buried 
_LC8_F42 = LCELL( _EQ046);
  _EQ046 = !_LC4_F42 &  _LC8_F42
         #  _LC4_F42 &  N10 & !N20
         #  _LC4_F42 & !N10 &  N20;



Project Information                                        e:\cal\b16jiafa.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:06
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:07


Memory Allocated
-----------------

Peak memory allocated during compilation  = 62,533K