b16jiafa.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 1,020 行 · 第 1/4 页
RPT
1,020 行
125 - - F -- INPUT ^ 0 0 0 2 N12
187 - - - 28 INPUT ^ 0 0 0 2 N13
186 - - - 27 INPUT ^ 0 0 0 2 N14
134 - - D -- INPUT ^ 0 0 0 2 N15
204 - - - 49 INPUT ^ 0 0 0 2 N16
73 - - - 29 INPUT ^ 0 0 0 2 N17
75 - - - 27 INPUT ^ 0 0 0 2 N18
55 - - - 48 INPUT ^ 0 0 0 2 N19
182 - - - -- INPUT ^ 0 0 0 3 N20
79 - - - -- INPUT ^ 0 0 0 2 N21
127 - - F -- INPUT ^ 0 0 0 2 N22
206 - - - 50 INPUT ^ 0 0 0 2 N23
133 - - D -- INPUT ^ 0 0 0 2 N24
200 - - - 46 INPUT ^ 0 0 0 2 N25
135 - - D -- INPUT ^ 0 0 0 2 N26
16 - - D -- INPUT ^ 0 0 0 2 N27
61 - - - 40 INPUT ^ 0 0 0 2 N28
57 - - - 43 INPUT ^ 0 0 0 2 N29
12 - - B -- INPUT ^ 0 0 0 2 N110
11 - - B -- INPUT ^ 0 0 0 2 N111
144 - - B -- INPUT ^ 0 0 0 2 N112
96 - - - 08 INPUT ^ 0 0 0 2 N113
97 - - - 07 INPUT ^ 0 0 0 2 N114
44 - - K -- INPUT ^ 0 0 0 1 N115
13 - - B -- INPUT ^ 0 0 0 2 N210
142 - - B -- INPUT ^ 0 0 0 2 N211
180 - - - 26 INPUT ^ 0 0 0 2 N212
89 - - - 18 INPUT ^ 0 0 0 2 N213
102 - - - 03 INPUT ^ 0 0 0 2 N214
41 - - K -- INPUT ^ 0 0 0 1 N215
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\b16jiafa.rpt
b16jiafa
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - F -- OUTPUT 0 1 0 0 CO0
27 - - F -- OUTPUT 0 1 0 0 CO1
17 - - D -- OUTPUT 0 1 0 0 CO2
193 - - - 38 OUTPUT 0 1 0 0 CO3
192 - - - 37 OUTPUT 0 1 0 0 CO4
18 - - D -- OUTPUT 0 1 0 0 CO5
207 - - - 51 OUTPUT 0 1 0 0 CO6
45 - - L -- OUTPUT 0 1 0 0 CO7
63 - - - 35 OUTPUT 0 1 0 0 CO8
19 - - D -- OUTPUT 0 1 0 0 CO9
26 - - F -- OUTPUT 0 1 0 0 CO10
147 - - B -- OUTPUT 0 1 0 0 CO11
143 - - B -- OUTPUT 0 1 0 0 CO12
163 - - - 14 OUTPUT 0 1 0 0 CO13
113 - - K -- OUTPUT 0 1 0 0 CO14
114 - - K -- OUTPUT 0 1 0 0 CO15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\b16jiafa.rpt
b16jiafa
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - F 42 OR2 4 0 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry1
- 3 - F 42 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry2
- 6 - D 37 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry3
- 1 - D 37 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry4
- 3 - D 52 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry5
- 1 - D 52 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry6
- 4 - D 36 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry7
- 7 - D 36 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry8
- 2 - D 36 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry9
- 4 - B 04 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry10
- 7 - B 04 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry11
- 3 - B 04 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry12
- 3 - K 13 OR2 2 1 0 2 |LPM_ADD_SUB:139|addcore:adder|pcarry13
- 7 - K 13 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|pcarry14
- 5 - F 42 OR2 s 3 0 0 1 |LPM_ADD_SUB:139|addcore:adder|~178~1
- 1 - F 42 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:179
- 5 - D 37 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:180
- 7 - D 37 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:181
- 2 - D 52 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:182
- 4 - D 52 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:183
- 1 - D 36 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:184
- 5 - D 36 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:185
- 8 - D 36 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:186
- 2 - B 04 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:187
- 5 - B 04 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:188
- 8 - B 04 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:189
- 2 - K 13 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:190
- 4 - K 13 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:191
- 8 - K 13 OR2 2 1 0 1 |LPM_ADD_SUB:139|addcore:adder|:192
- 4 - F 42 AND2 2 0 0 2 :58
- 1 - K 13 OR2 2 1 1 0 :181
- 5 - K 13 OR2 2 1 1 0 :187
- 6 - K 13 OR2 2 1 1 0 :193
- 6 - B 04 OR2 2 1 1 0 :199
- 1 - B 04 OR2 2 1 1 0 :205
- 2 - F 42 OR2 2 1 1 0 :211
- 6 - D 36 OR2 2 1 1 0 :217
- 3 - D 36 OR2 2 1 1 0 :223
- 3 - D 37 OR2 2 1 1 0 :229
- 5 - D 52 OR2 2 1 1 0 :235
- 6 - D 52 OR2 2 1 1 0 :241
- 2 - D 37 OR2 2 1 1 0 :247
- 8 - D 37 OR2 2 1 1 0 :253
- 4 - D 37 OR2 2 1 1 0 :259
- 6 - F 42 OR2 1 2 1 0 :265
- 8 - F 42 OR2 2 1 1 0 :271
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cal\b16jiafa.rpt
b16jiafa
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 7/208( 3%) 2/104( 1%) 0/104( 0%) 5/16( 31%) 2/16( 12%) 0/16( 0%)
C: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 8/208( 3%) 0/104( 0%) 14/104( 13%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 5/208( 2%) 0/104( 0%) 1/104( 0%) 2/16( 12%) 3/16( 18%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 2/208( 0%) 7/104( 6%) 0/104( 0%) 2/16( 12%) 2/16( 12%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
27: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
29: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
38: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
49: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
50: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
51: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cal\b16jiafa.rpt
b16jiafa
** EQUATIONS **
ADD : INPUT;
EQUAL : INPUT;
N10 : INPUT;
N11 : INPUT;
N12 : INPUT;
N13 : INPUT;
N14 : INPUT;
N15 : INPUT;
N16 : INPUT;
N17 : INPUT;
N18 : INPUT;
N19 : INPUT;
N20 : INPUT;
N21 : INPUT;
N22 : INPUT;
N23 : INPUT;
N24 : INPUT;
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