reg.hif

ProtelDXp 实现计算器功能

HIF003
--
-- Copyright (C) 1988-2002 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera.  Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner.  Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors.  No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
--
-- Warning: do not edit this file!
--
FILES
{
	reg1.gdf
	{
		reg1 [] []
		{
			2 [] [];
		}
	}
	1to4.tdf
	{
		1to4 [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			4 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [b3,b2,b1,b0,a0,a1,a2,a3];
		}
	}
	4to1.tdf
	{
		4to1 [USE_LPM_FOR_AHDL_OPERATORS] []
		{
			3 [USE_LPM_FOR_AHDL_OPERATORS=OFF] [b0,b1,b2,b3,a3,a2,a1,a0];
		}
	}
	reg4.gdf
	{
		reg4 [] []
		{
			1 [] [];
		}
	}
	reg.gdf
	{
		reg [] []
		{
			0 [] [];
		}
	}
}
TREE
{
	reg::(0,0):(0): reg.gdf
	{
		1to4::(0,0):(6): 1to4.tdf;
		4to1::(0,0):(7): 4to1.tdf;
		4to1::(0,0):(8): 4to1.tdf;
		4to1::(0,0):(9): 4to1.tdf;
		4to1::(0,0):(10): 4to1.tdf;
		reg4::(0,0):(11): reg4.gdf
		{
			reg1:2:(0,0):(1): reg1.gdf;
			reg1:2:(0,0):(2): reg1.gdf;
			reg1:2:(0,0):(3): reg1.gdf;
			reg1:2:(0,0):(4): reg1.gdf;
		}
	}
}