control1.rpt

来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 732 行 · 第 1/3 页

-- Equation name is 'outa2', type is output 
outa2    =  _LC7_A46;

-- Node name is 'outa3' from file "control1.tdf" line 15, column 5
-- Equation name is 'outa3', type is output 
outa3    =  _LC8_A46;

-- Node name is 'outb0' from file "control1.tdf" line 16, column 5
-- Equation name is 'outb0', type is output 
outb0    =  _LC5_A46;

-- Node name is 'outb1' from file "control1.tdf" line 16, column 5
-- Equation name is 'outb1', type is output 
outb1    =  _LC1_A46;

-- Node name is 'outb2' from file "control1.tdf" line 16, column 5
-- Equation name is 'outb2', type is output 
outb2    =  _LC4_A46;

-- Node name is 'outb3' from file "control1.tdf" line 16, column 5
-- Equation name is 'outb3', type is output 
outb3    =  _LC3_A46;

-- Node name is 'outc0' from file "control1.tdf" line 17, column 5
-- Equation name is 'outc0', type is output 
outc0    =  _LC3_F10;

-- Node name is 'outc1' from file "control1.tdf" line 17, column 5
-- Equation name is 'outc1', type is output 
outc1    =  _LC1_F10;

-- Node name is 'outc2' from file "control1.tdf" line 17, column 5
-- Equation name is 'outc2', type is output 
outc2    =  _LC5_F10;

-- Node name is 'outc3' from file "control1.tdf" line 17, column 5
-- Equation name is 'outc3', type is output 
outc3    =  _LC7_F10;

-- Node name is 'outd0' from file "control1.tdf" line 18, column 5
-- Equation name is 'outd0', type is output 
outd0    =  _LC8_F10;

-- Node name is 'outd1' from file "control1.tdf" line 18, column 5
-- Equation name is 'outd1', type is output 
outd1    =  _LC4_F10;

-- Node name is 'outd2' from file "control1.tdf" line 18, column 5
-- Equation name is 'outd2', type is output 
outd2    =  _LC2_F10;

-- Node name is 'outd3' from file "control1.tdf" line 18, column 5
-- Equation name is 'outd3', type is output 
outd3    =  _LC6_F10;

-- Node name is ':94' from file "control1.tdf" line 15, column 7
-- Equation name is '_LC2_A46', type is buried 
_LC2_A46 = LCELL( _EQ001);
  _EQ001 = !con &  opa10
         #  con &  opa20;

-- Node name is ':97' from file "control1.tdf" line 15, column 7
-- Equation name is '_LC6_A46', type is buried 
_LC6_A46 = LCELL( _EQ002);
  _EQ002 = !con &  opa11
         #  con &  opa21;

-- Node name is ':100' from file "control1.tdf" line 15, column 7
-- Equation name is '_LC7_A46', type is buried 
_LC7_A46 = LCELL( _EQ003);
  _EQ003 = !con &  opa12
         #  con &  opa22;

-- Node name is ':103' from file "control1.tdf" line 15, column 7
-- Equation name is '_LC8_A46', type is buried 
_LC8_A46 = LCELL( _EQ004);
  _EQ004 = !con &  opa13
         #  con &  opa23;

-- Node name is ':106' from file "control1.tdf" line 16, column 7
-- Equation name is '_LC5_A46', type is buried 
_LC5_A46 = LCELL( _EQ005);
  _EQ005 = !con &  opb10
         #  con &  opb20;

-- Node name is ':109' from file "control1.tdf" line 16, column 7
-- Equation name is '_LC1_A46', type is buried 
_LC1_A46 = LCELL( _EQ006);
  _EQ006 = !con &  opb11
         #  con &  opb21;

-- Node name is ':112' from file "control1.tdf" line 16, column 7
-- Equation name is '_LC4_A46', type is buried 
_LC4_A46 = LCELL( _EQ007);
  _EQ007 = !con &  opb12
         #  con &  opb22;

-- Node name is ':115' from file "control1.tdf" line 16, column 7
-- Equation name is '_LC3_A46', type is buried 
_LC3_A46 = LCELL( _EQ008);
  _EQ008 = !con &  opb13
         #  con &  opb23;

-- Node name is ':118' from file "control1.tdf" line 17, column 7
-- Equation name is '_LC3_F10', type is buried 
_LC3_F10 = LCELL( _EQ009);
  _EQ009 = !con &  opc10
         #  con &  opc20;

-- Node name is ':121' from file "control1.tdf" line 17, column 7
-- Equation name is '_LC1_F10', type is buried 
_LC1_F10 = LCELL( _EQ010);
  _EQ010 = !con &  opc11
         #  con &  opc21;

-- Node name is ':124' from file "control1.tdf" line 17, column 7
-- Equation name is '_LC5_F10', type is buried 
_LC5_F10 = LCELL( _EQ011);
  _EQ011 = !con &  opc12
         #  con &  opc22;

-- Node name is ':127' from file "control1.tdf" line 17, column 7
-- Equation name is '_LC7_F10', type is buried 
_LC7_F10 = LCELL( _EQ012);
  _EQ012 = !con &  opc13
         #  con &  opc23;

-- Node name is ':130' from file "control1.tdf" line 18, column 7
-- Equation name is '_LC8_F10', type is buried 
_LC8_F10 = LCELL( _EQ013);
  _EQ013 = !con &  opd10
         #  con &  opd20;

-- Node name is ':133' from file "control1.tdf" line 18, column 7
-- Equation name is '_LC4_F10', type is buried 
_LC4_F10 = LCELL( _EQ014);
  _EQ014 = !con &  opd11
         #  con &  opd21;

-- Node name is ':136' from file "control1.tdf" line 18, column 7
-- Equation name is '_LC2_F10', type is buried 
_LC2_F10 = LCELL( _EQ015);
  _EQ015 = !con &  opd12
         #  con &  opd22;

-- Node name is ':139' from file "control1.tdf" line 18, column 7
-- Equation name is '_LC6_F10', type is buried 
_LC6_F10 = LCELL( _EQ016);
  _EQ016 = !con &  opd13
         #  con &  opd23;



Project Information                                        e:\cal\control1.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 52,479K