b16jiafa.vhd

来自「ProtelDXp 实现计算器功能」· VHDL 代码 · 共 25 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY B16JIAFA IS
PORT
(
		ADD,EQUAL	:IN STD_LOGIC;
	
		N1,N2	:IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		CO	:OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
END;
ARCHITECTURE A OF B16JIAFA IS
BEGIN
	PROCESS(ADD,EQUAL)
BEGIN
	IF ADD='1'AND EQUAL='1'THEN
		CO<=N1+N2;
	END IF;
END PROCESS;
END;