📄 reg.rpt
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CLR : INPUT;
INCLK : INPUT;
OUTCODE0 : INPUT;
OUTCODE1 : INPUT;
OUTCODE2 : INPUT;
OUTCODE3 : INPUT;
-- Node name is 'A0'
-- Equation name is 'A0', type is output
A0 = _LC1_B49;
-- Node name is 'A1'
-- Equation name is 'A1', type is output
A1 = _LC2_F14;
-- Node name is 'A2'
-- Equation name is 'A2', type is output
A2 = _LC1_H21;
-- Node name is 'A3'
-- Equation name is 'A3', type is output
A3 = _LC6_D31;
-- Node name is 'B0'
-- Equation name is 'B0', type is output
B0 = _LC8_B49;
-- Node name is 'B1'
-- Equation name is 'B1', type is output
B1 = _LC7_F14;
-- Node name is 'B2'
-- Equation name is 'B2', type is output
B2 = _LC5_H21;
-- Node name is 'B3'
-- Equation name is 'B3', type is output
B3 = _LC4_D31;
-- Node name is 'C0'
-- Equation name is 'C0', type is output
C0 = _LC6_B49;
-- Node name is 'C1'
-- Equation name is 'C1', type is output
C1 = _LC3_F14;
-- Node name is 'C2'
-- Equation name is 'C2', type is output
C2 = _LC6_H21;
-- Node name is 'C3'
-- Equation name is 'C3', type is output
C3 = _LC2_D31;
-- Node name is 'D0'
-- Equation name is 'D0', type is output
D0 = _LC4_B49;
-- Node name is 'D1'
-- Equation name is 'D1', type is output
D1 = _LC5_F14;
-- Node name is 'D2'
-- Equation name is 'D2', type is output
D2 = _LC8_H21;
-- Node name is 'D3'
-- Equation name is 'D3', type is output
D3 = _LC7_D31;
-- Node name is '|reg4:11|reg1:1|:1' = '|reg4:11|reg1:1|Q0'
-- Equation name is '_LC1_B49', type is buried
_LC1_B49 = DFFE( OUTCODE0, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:1|:3' = '|reg4:11|reg1:1|Q1'
-- Equation name is '_LC2_F14', type is buried
_LC2_F14 = DFFE( OUTCODE1, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:1|:4' = '|reg4:11|reg1:1|Q2'
-- Equation name is '_LC1_H21', type is buried
_LC1_H21 = DFFE( OUTCODE2, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:1|:5' = '|reg4:11|reg1:1|Q3'
-- Equation name is '_LC6_D31', type is buried
_LC6_D31 = DFFE( OUTCODE3, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:2|:1' = '|reg4:11|reg1:2|Q0'
-- Equation name is '_LC8_B49', type is buried
_LC8_B49 = DFFE( _LC1_B49, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:2|:3' = '|reg4:11|reg1:2|Q1'
-- Equation name is '_LC7_F14', type is buried
_LC7_F14 = DFFE( _LC2_F14, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:2|:4' = '|reg4:11|reg1:2|Q2'
-- Equation name is '_LC5_H21', type is buried
_LC5_H21 = DFFE( _LC1_H21, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:2|:5' = '|reg4:11|reg1:2|Q3'
-- Equation name is '_LC4_D31', type is buried
_LC4_D31 = DFFE( _LC6_D31, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:3|:1' = '|reg4:11|reg1:3|Q0'
-- Equation name is '_LC6_B49', type is buried
_LC6_B49 = DFFE( _LC8_B49, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:3|:3' = '|reg4:11|reg1:3|Q1'
-- Equation name is '_LC3_F14', type is buried
_LC3_F14 = DFFE( _LC7_F14, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:3|:4' = '|reg4:11|reg1:3|Q2'
-- Equation name is '_LC6_H21', type is buried
_LC6_H21 = DFFE( _LC5_H21, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:3|:5' = '|reg4:11|reg1:3|Q3'
-- Equation name is '_LC2_D31', type is buried
_LC2_D31 = DFFE( _LC4_D31, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:4|:1' = '|reg4:11|reg1:4|Q0'
-- Equation name is '_LC4_B49', type is buried
_LC4_B49 = DFFE( _LC6_B49, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:4|:3' = '|reg4:11|reg1:4|Q1'
-- Equation name is '_LC5_F14', type is buried
_LC5_F14 = DFFE( _LC3_F14, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:4|:4' = '|reg4:11|reg1:4|Q2'
-- Equation name is '_LC8_H21', type is buried
_LC8_H21 = DFFE( _LC6_H21, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
-- Node name is '|reg4:11|reg1:4|:5' = '|reg4:11|reg1:4|Q3'
-- Equation name is '_LC7_D31', type is buried
_LC7_D31 = DFFE( _LC2_D31, GLOBAL( INCLK), GLOBAL( CLR), VCC, VCC);
Project Information e:\cal\reg.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:05
Memory Allocated
-----------------
Peak memory allocated during compilation = 56,669K
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