add16.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 986 行 · 第 1/4 页
RPT
986 行
10 - - A -- INPUT ^ 0 0 0 2 a10
193 - - - 38 INPUT ^ 0 0 0 2 a11
166 - - - 15 INPUT ^ 0 0 0 2 a12
141 - - C -- INPUT ^ 0 0 0 2 a13
87 - - - 21 INPUT ^ 0 0 0 2 a14
140 - - C -- INPUT ^ 0 0 0 2 a15
182 - - - -- INPUT ^ 0 0 0 2 b0
79 - - - -- INPUT ^ 0 0 0 2 b1
16 - - D -- INPUT ^ 0 0 0 2 b2
67 - - - 33 INPUT ^ 0 0 0 2 b3
206 - - - 50 INPUT ^ 0 0 0 2 b4
13 - - B -- INPUT ^ 0 0 0 2 b5
69 - - - 32 INPUT ^ 0 0 0 2 b6
205 - - - 50 INPUT ^ 0 0 0 2 b7
150 - - A -- INPUT ^ 0 0 0 2 b8
56 - - - 45 INPUT ^ 0 0 0 2 b9
148 - - A -- INPUT ^ 0 0 0 2 b10
55 - - - 48 INPUT ^ 0 0 0 2 b11
93 - - - 14 INPUT ^ 0 0 0 2 b12
157 - - - 09 INPUT ^ 0 0 0 2 b13
86 - - - 23 INPUT ^ 0 0 0 2 b14
159 - - - 11 INPUT ^ 0 0 0 2 b15
78 - - - -- INPUT ^ 0 0 0 3 ci
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\electron\bcdto2\add16.rpt
add16
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
119 - - H -- OUTPUT 0 1 0 0 co0
18 - - D -- OUTPUT 0 1 0 0 co1
71 - - - 30 OUTPUT 0 1 0 0 co2
19 - - D -- OUTPUT 0 1 0 0 co3
73 - - - 29 OUTPUT 0 1 0 0 co4
12 - - B -- OUTPUT 0 1 0 0 co5
147 - - B -- OUTPUT 0 1 0 0 co6
197 - - - 43 OUTPUT 0 1 0 0 co7
36 - - H -- OUTPUT 0 1 0 0 co8
7 - - A -- OUTPUT 0 1 0 0 co9
8 - - A -- OUTPUT 0 1 0 0 co10
62 - - - 36 OUTPUT 0 1 0 0 co11
47 - - L -- OUTPUT 0 1 0 0 co12
15 - - C -- OUTPUT 0 1 0 0 co13
94 - - - 13 OUTPUT 0 1 0 0 co14
164 - - - 14 OUTPUT 0 1 0 0 co15
14 - - C -- OUTPUT 0 1 0 0 co16
17 - - D -- OUTPUT 0 1 0 0 c0
189 - - - 30 OUTPUT 0 1 0 0 c1
134 - - D -- OUTPUT 0 1 0 0 c2
44 - - K -- OUTPUT 0 1 0 0 c3
198 - - - 44 OUTPUT 0 1 0 0 c4
57 - - - 43 OUTPUT 0 1 0 0 c5
143 - - B -- OUTPUT 0 1 0 0 c6
40 - - J -- OUTPUT 0 1 0 0 c7
9 - - A -- OUTPUT 0 1 0 0 c8
63 - - - 35 OUTPUT 0 1 0 0 c9
191 - - - 35 OUTPUT 0 1 0 0 c10
64 - - - 35 OUTPUT 0 1 0 0 c11
162 - - - 13 OUTPUT 0 1 0 0 c12
139 - - C -- OUTPUT 0 1 0 0 c13
136 - - C -- OUTPUT 0 1 0 0 c14
163 - - - 14 OUTPUT 0 1 0 0 c15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\electron\bcdto2\add16.rpt
add16
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 8 - H 02 LCELL s 1 0 1 0 co0~1
- 4 - D 29 OR2 3 0 1 0 :94
- 6 - D 29 OR2 3 0 1 2 :98
- 1 - D 29 OR2 2 1 1 0 :100
- 2 - D 29 OR2 2 1 1 2 :104
- 5 - D 29 OR2 2 1 1 0 :106
- 7 - D 29 OR2 2 1 1 2 :110
- 8 - D 29 OR2 2 1 1 0 :112
- 3 - D 29 OR2 2 1 1 2 :116
- 5 - B 43 OR2 2 1 1 0 :118
- 4 - B 43 OR2 2 1 1 2 :122
- 2 - B 43 OR2 2 1 1 0 :124
- 1 - B 43 OR2 2 1 1 2 :128
- 6 - B 43 OR2 2 1 1 0 :130
- 3 - B 43 OR2 2 1 1 2 :134
- 7 - B 43 OR2 2 1 1 0 :136
- 8 - B 43 OR2 2 1 1 2 :140
- 4 - A 35 OR2 2 1 1 0 :142
- 1 - A 35 OR2 2 1 1 2 :146
- 5 - A 35 OR2 2 1 1 0 :148
- 2 - A 35 OR2 2 1 1 2 :152
- 3 - A 35 OR2 2 1 1 0 :154
- 6 - A 35 OR2 2 1 1 2 :158
- 7 - A 35 OR2 2 1 1 0 :160
- 8 - A 35 OR2 2 1 1 2 :164
- 1 - C 13 OR2 2 1 1 0 :166
- 7 - C 13 OR2 2 1 1 2 :170
- 5 - C 13 OR2 2 1 1 0 :172
- 2 - C 13 OR2 2 1 1 2 :176
- 8 - C 13 OR2 2 1 1 0 :178
- 6 - C 13 OR2 2 1 1 2 :182
- 4 - C 13 OR2 2 1 1 0 :184
- 3 - C 13 OR2 2 1 1 0 :188
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\electron\bcdto2\add16.rpt
add16
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/208( 1%) 0/104( 0%) 8/104( 7%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
B: 6/208( 2%) 0/104( 0%) 6/104( 5%) 4/16( 25%) 3/16( 18%) 0/16( 0%)
C: 5/208( 2%) 8/104( 7%) 0/104( 0%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
D: 5/208( 2%) 0/104( 0%) 2/104( 1%) 2/16( 12%) 4/16( 25%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 1/104( 0%) 1/104( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 1/104( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
14: 3/24( 12%) 1/4( 25%) 2/4( 50%) 0/4( 0%)
15: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
30: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 4/24( 16%) 0/4( 0%) 3/4( 75%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
44: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
45: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
51: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
52: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\electron\bcdto2\add16.rpt
add16
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
a8 : INPUT;
a9 : INPUT;
a10 : INPUT;
a11 : INPUT;
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