div16.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 827 行 · 第 1/5 页
RPT
827 行
Average fan-in: 3.34/4 ( 83%)
Total fan-in: 1494/19968 ( 7%)
Total input pins required: 34
Total input I/O cell registers required: 0
Total output pins required: 33
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 447
Total flipflops required: 0
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 14/4992 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 EA 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 8 8 8 2 8 7 8 0 0 0 8 2 6 7 7 0 0 8 8 0 0 8 8 0 0 8 127/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 8 8 7 8 0 8 8 0 3 8 0 0 0 3 7 0 8 0 8 0 0 0 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 0 8 0 0 0 0 0 0 124/0
G: 8 0 0 8 0 8 8 8 8 8 1 8 8 0 8 0 0 8 0 8 0 8 8 8 8 0 0 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 145/0
H: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
I: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
J: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
K: 0 0 8 8 0 0 8 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 40/0
L: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 8 8 24 23 8 8 24 16 8 11 9 8 8 0 19 7 0 24 0 19 0 8 8 16 24 8 0 16 8 16 2 8 7 8 0 0 0 8 10 6 7 7 0 0 8 8 8 0 8 8 0 0 8 447/0
Device-Specific Information: e:\cal\div16.rpt
div16
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
175 - - - 22 INPUT ^ 0 0 0 4 a0
44 - - K -- INPUT ^ 0 0 0 2 a1
114 - - K -- INPUT ^ 0 0 0 2 a2
97 - - - 07 INPUT ^ 0 0 0 4 a3
27 - - F -- INPUT ^ 0 0 0 2 a4
127 - - F -- INPUT ^ 0 0 0 2 a5
126 - - F -- INPUT ^ 0 0 0 2 a6
68 - - - 33 INPUT ^ 0 0 0 2 a7
53 - - - 52 INPUT ^ 0 0 0 2 a8
187 - - - 28 INPUT ^ 0 0 0 2 a9
67 - - - 33 INPUT ^ 0 0 0 2 a10
150 - - A -- INPUT ^ 0 0 0 2 a11
64 - - - 35 INPUT ^ 0 0 0 3 a12
10 - - A -- INPUT ^ 0 0 0 2 a13
149 - - A -- INPUT ^ 0 0 0 3 a14
8 - - A -- INPUT ^ 0 0 0 3 a15
170 - - - 19 INPUT ^ 0 0 0 37 b0
183 - - - -- INPUT ^ 0 0 0 45 b1
78 - - - -- INPUT ^ 0 0 0 45 b2
80 - - - -- INPUT ^ 0 0 0 40 b3
184 - - - -- INPUT ^ 0 0 0 37 b4
182 - - - -- INPUT ^ 0 0 0 35 b5
79 - - - -- INPUT ^ 0 0 0 31 b6
159 - - - 11 INPUT ^ 0 0 0 28 b7
26 - - F -- INPUT ^ 0 0 0 25 b8
54 - - - 51 INPUT ^ 0 0 0 23 b9
174 - - - 22 INPUT ^ 0 0 0 19 b10
161 - - - 12 INPUT ^ 0 0 0 15 b11
104 - - - 01 INPUT ^ 0 0 0 13 b12
95 - - - 09 INPUT ^ 0 0 0 10 b13
172 - - - 20 INPUT ^ 0 0 0 8 b14
168 - - - 17 INPUT ^ 0 0 0 6 b15
100 - - - 05 INPUT ^ 0 0 0 33 dent
92 - - - 15 INPUT ^ 0 0 0 33 div
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\div16.rpt
div16
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
166 - - - 15 OUTPUT 0 1 0 0 err
116 - - I -- OUTPUT 0 1 0 0 rest0
134 - - D -- OUTPUT 0 1 0 0 rest1
135 - - D -- OUTPUT 0 1 0 0 rest2
17 - - D -- OUTPUT 0 1 0 0 rest3
120 - - H -- OUTPUT 0 1 0 0 rest4
180 - - - 26 OUTPUT 0 1 0 0 rest5
128 - - E -- OUTPUT 0 1 0 0 rest6
173 - - - 21 OUTPUT 0 1 0 0 rest7
148 - - A -- OUTPUT 0 1 0 0 rest8
121 - - G -- OUTPUT 0 1 0 0 rest9
75 - - - 27 OUTPUT 0 1 0 0 rest10
73 - - - 29 OUTPUT 0 1 0 0 rest11
189 - - - 30 OUTPUT 0 1 0 0 rest12
83 - - - 25 OUTPUT 0 1 0 0 rest13
102 - - - 03 OUTPUT 0 1 0 0 rest14
111 - - L -- OUTPUT 0 1 0 0 rest15
86 - - - 23 OUTPUT 0 1 0 0 y0
16 - - D -- OUTPUT 0 1 0 0 y1
200 - - - 46 OUTPUT 0 1 0 0 y2
85 - - - 24 OUTPUT 0 1 0 0 y3
177 - - - 24 OUTPUT 0 1 0 0 y4
125 - - F -- OUTPUT 0 1 0 0 y5
179 - - - 25 OUTPUT 0 1 0 0 y6
9 - - A -- OUTPUT 0 1 0 0 y7
198 - - - 44 OUTPUT 0 1 0 0 y8
7 - - A -- OUTPUT 0 1 0 0 y9
29 - - G -- OUTPUT 0 1 0 0 y10
133 - - D -- OUTPUT 0 1 0 0 y11
199 - - - 45 OUTPUT 0 1 0 0 y12
192 - - - 37 OUTPUT 0 1 0 0 y13
28 - - G -- OUTPUT 0 1 0 0 y14
176 - - - 23 OUTPUT 0 1 0 0 y15
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\div16.rpt
div16
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 15 OR2 4 0 0 2 |LPM_ADD_SUB:3040|addcore:adder|:336
- 6 - A 27 OR2 2 0 0 3 |LPM_ADD_SUB:4692|addcore:adder|pcarry13
- 8 - A 27 OR2 1 2 0 1 |LPM_ADD_SUB:4692|addcore:adder|pcarry14
- 3 - F 10 OR2 2 0 0 1 |LPM_ADD_SUB:5518|addcore:adder|pcarry3
- 5 - F 16 OR2 4 0 0 2 |LPM_ADD_SUB:5518|addcore:adder|pcarry4
- 6 - F 16 OR2 2 1 0 2 |LPM_ADD_SUB:5518|addcore:adder|pcarry5
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