div16.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 827 行 · 第 1/5 页
RPT
827 行
/ 208 206 204 202 200 198 196 194 192 190 188 186 184 182 180 178 176 174 172 170 168 166 164 162 160 158 |_
/ 207 205 203 201 199 197 195 193 191 189 187 185 183 181 179 177 175 173 171 169 167 165 163 161 159 157 |
#TCK | 1 156 | ^DATA0
^CONF_DONE | 2 155 | ^DCLK
^nCEO | 3 154 | ^nCE
#TDO | 4 153 | #TDI
VCCIO | 5 152 | VCCINT
GND | 6 151 | GND
y9 | 7 150 | a11
a15 | 8 149 | a14
y7 | 9 148 | rest8
a13 | 10 147 | RESERVED
RESERVED | 11 146 | VCCIO
RESERVED | 12 145 | GND
RESERVED | 13 144 | RESERVED
RESERVED | 14 143 | RESERVED
RESERVED | 15 142 | RESERVED
y1 | 16 141 | RESERVED
rest3 | 17 140 | RESERVED
RESERVED | 18 139 | RESERVED
RESERVED | 19 138 | VCCIO
GND | 20 137 | GND
VCCINT | 21 136 | RESERVED
VCCIO | 22 135 | rest2
GND | 23 134 | rest1
RESERVED | 24 133 | y11
RESERVED | 25 132 | RESERVED
b8 | 26 131 | RESERVED
a4 | 27 EP1K100QC208-3 130 | VCCINT
y14 | 28 129 | GND
y10 | 29 128 | rest6
RESERVED | 30 127 | a5
RESERVED | 31 126 | a6
GND | 32 125 | y5
VCCINT | 33 124 | VCCINT
VCCIO | 34 123 | GND
GND | 35 122 | RESERVED
RESERVED | 36 121 | rest9
RESERVED | 37 120 | rest4
RESERVED | 38 119 | RESERVED
RESERVED | 39 118 | VCCIO
RESERVED | 40 117 | GND
RESERVED | 41 116 | rest0
VCCIO | 42 115 | RESERVED
GND | 43 114 | a2
a1 | 44 113 | RESERVED
RESERVED | 45 112 | RESERVED
RESERVED | 46 111 | rest15
RESERVED | 47 110 | VCCIO
VCCINT | 48 109 | GND
GND | 49 108 | ^MSEL0
#TMS | 50 107 | ^MSEL1
#TRST | 51 106 | VCCINT
^nSTATUS | 52 105 | ^nCONFIG
| 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 _|
\ 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 |
\-----------------------------------------------------------------------------------------------------------
a b R R R R G R R R R a R V a a R R R V r R r G V b b b G G r V y y R R R R V d R R b R a V R d R r R b
8 9 E E E E N E E E E 1 E C 1 7 E E E C e E e N C 2 6 3 N N e C 3 0 E E E E C i E E 1 E 3 C E e E e E 1
S S S S D S S S S 2 S C 0 S S S C s S s D C D D s C S S S S C v S S 3 S C S n S s S 2
E E E E E E E E E I E E E I t E t I t I E E E E I E E E I E t E t E
R R R R R R R R R O R R R N 1 R 1 N 1 O R R R R N R R R O R R 1 R
V V V V V V V V V V V V T 1 V 0 T 3 V V V V T V V V V V 4 V
E E E E E E E E E E E E E E E E E E E E E E E
D D D D D D D D D D D D D D D D D D D D D D D
N.C. = No Connect. This pin has no internal connection to the device.
VCCINT = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
VCCIO = Dedicated power pin, which MUST be connected to VCC (2.5 volts).
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
^ = Dedicated configuration pin.
+ = Reserved configuration pin, which is tri-stated during user mode.
* = Reserved configuration pin, which drives out in user mode.
PDn = Power Down pin.
@ = Special-purpose pin.
# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.
& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.
$ = Pin has PCI I/O option enabled. Pin is neither '5.0 V'- nor '3.3 V'-tolerant.
Device-Specific Information: e:\cal\div16.rpt
div16
** RESOURCE USAGE **
Logic Column Row
Array Interconnect Interconnect Clears/ External
Block Logic Cells Driven Driven Clocks Presets Interconnect
A15 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/26( 34%)
A27 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/26( 30%)
A28 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 9/26( 34%)
A29 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 11/26( 42%)
A30 2/ 8( 25%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 2/26( 7%)
A31 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 11/26( 42%)
A32 7/ 8( 87%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 11/26( 42%)
A33 8/ 8(100%) 3/ 8( 37%) 3/ 8( 37%) 0/2 0/2 9/26( 34%)
A37 8/ 8(100%) 2/ 8( 25%) 5/ 8( 62%) 0/2 0/2 11/26( 42%)
A38 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 4/26( 15%)
A39 6/ 8( 75%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 6/26( 23%)
A40 7/ 8( 87%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
A41 7/ 8( 87%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 14/26( 53%)
A44 8/ 8(100%) 3/ 8( 37%) 2/ 8( 25%) 0/2 0/2 16/26( 61%)
A45 8/ 8(100%) 2/ 8( 25%) 4/ 8( 50%) 0/2 0/2 12/26( 46%)
A48 8/ 8(100%) 1/ 8( 12%) 4/ 8( 50%) 0/2 0/2 10/26( 38%)
A49 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 13/26( 50%)
A52 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/26( 53%)
D3 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 10/26( 38%)
D20 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 6/26( 23%)
F2 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
F3 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
F4 7/ 8( 87%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 14/26( 53%)
F5 8/ 8(100%) 5/ 8( 62%) 0/ 8( 0%) 0/2 0/2 10/26( 38%)
F7 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 18/26( 69%)
F8 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 11/26( 42%)
F10 3/ 8( 37%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 5/26( 19%)
F11 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 8/26( 30%)
F15 3/ 8( 37%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 7/26( 26%)
F16 7/ 8( 87%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 10/26( 38%)
F18 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
F20 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/26( 34%)
F24 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 10/26( 38%)
F25 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 17/26( 65%)
F26 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
F38 8/ 8(100%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 15/26( 57%)
F46 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 11/26( 42%)
G1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 11/26( 42%)
G4 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 11/26( 42%)
G6 8/ 8(100%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 17/26( 65%)
G7 8/ 8(100%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 17/26( 65%)
G8 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
G9 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 17/26( 65%)
G10 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 11/26( 42%)
G11 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/26( 7%)
G12 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
G13 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/26( 42%)
G15 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 0/2 0/2 10/26( 38%)
G18 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 0/2 0/2 9/26( 34%)
G20 8/ 8(100%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 17/26( 65%)
G22 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 10/26( 38%)
G23 8/ 8(100%) 6/ 8( 75%) 2/ 8( 25%) 0/2 0/2 13/26( 50%)
G24 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/26( 42%)
G25 8/ 8(100%) 4/ 8( 50%) 1/ 8( 12%) 0/2 0/2 10/26( 38%)
G27 8/ 8(100%) 1/ 8( 12%) 3/ 8( 37%) 0/2 0/2 10/26( 38%)
G29 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 13/26( 50%)
K3 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 9/26( 34%)
K4 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 13/26( 50%)
K7 8/ 8(100%) 5/ 8( 62%) 0/ 8( 0%) 0/2 0/2 10/26( 38%)
K18 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 10/26( 38%)
K25 8/ 8(100%) 2/ 8( 25%) 3/ 8( 37%) 0/2 0/2 10/26( 38%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 61/141 ( 43%)
Total logic cells used: 447/4992 ( 8%)
Total embedded cells used: 0/192 ( 0%)
Total EABs used: 0/12 ( 0%)
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