fp.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 788 行 · 第 1/3 页
RPT
788 行
_EQ012 = c11 & !_LC1_C22 & _LC1_F33
# !c11 & _LC1_C22 & _LC1_F33;
-- Node name is ':8' = 'c12'
-- Equation name is 'c12', location is LC5_F52, type is buried.
c12 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !c11 & c12 & _LC1_F33
# c12 & !_LC1_C22 & _LC1_F33
# c11 & !c12 & _LC1_C22 & _LC1_F33;
-- Node name is ':7' = 'c13'
-- Equation name is 'c13', location is LC6_F52, type is buried.
c13 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
_EQ014 = c13 & _LC1_F33 & !_LC8_F52
# !c13 & _LC1_F33 & _LC8_F52;
-- Node name is ':6' = 'c14'
-- Equation name is 'c14', location is LC3_F52, type is buried.
c14 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, VCC);
_EQ015 = !c13 & c14 & _LC1_F33
# c14 & _LC1_F33 & !_LC8_F52
# c13 & !c14 & _LC1_F33 & _LC8_F52;
-- Node name is ':5' = 'c15'
-- Equation name is 'c15', location is LC3_F33, type is buried.
c15 = DFFE( _EQ016, GLOBAL( clk), VCC, VCC, VCC);
_EQ016 = c15 & _LC1_F33 & !_LC2_F52
# !c15 & _LC1_F33 & _LC2_F52;
-- Node name is ':4' = 'c16'
-- Equation name is 'c16', location is LC4_F33, type is buried.
c16 = DFFE( _EQ017, GLOBAL( clk), VCC, VCC, VCC);
_EQ017 = !c15 & c16 & _LC1_F33
# c16 & _LC1_F33 & !_LC2_F52
# c15 & !c16 & _LC1_F33 & _LC2_F52;
-- Node name is ':3' = 'c17'
-- Equation name is 'c17', location is LC7_F33, type is buried.
c17 = DFFE( _EQ018, GLOBAL( clk), VCC, VCC, VCC);
_EQ018 = !c16 & c17 & _LC1_F33
# c17 & _LC1_F33 & !_LC6_F33
# c16 & !c17 & _LC1_F33 & _LC6_F33;
-- Node name is 'sec1'
-- Equation name is 'sec1', type is output
sec1 = _LC5_F33;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:119' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C23', type is buried
_LC5_C23 = LCELL( _EQ019);
_EQ019 = c0 & c1 & c2;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:127' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C23', type is buried
_LC1_C23 = LCELL( _EQ020);
_EQ020 = c3 & c4 & _LC5_C23;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:131' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_C25', type is buried
_LC3_C25 = LCELL( _EQ021);
_EQ021 = c5 & _LC1_C23;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:139' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_C22', type is buried
_LC5_C22 = LCELL( _EQ022);
_EQ022 = c5 & c6 & c7 & _LC1_C23;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:147' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C22', type is buried
_LC8_C22 = LCELL( _EQ023);
_EQ023 = c8 & c9 & _LC5_C22;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:151' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = LCELL( _EQ024);
_EQ024 = c8 & c9 & c10 & _LC5_C22;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:159' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_F52', type is buried
_LC8_F52 = LCELL( _EQ025);
_EQ025 = c11 & c12 & _LC1_C22;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:167' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_F52', type is buried
_LC2_F52 = LCELL( _EQ026);
_EQ026 = c13 & c14 & _LC8_F52;
-- Node name is '|LPM_ADD_SUB:167|addcore:adder|:171' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_F33', type is buried
_LC6_F33 = LCELL( _EQ027);
_EQ027 = c15 & _LC2_F52;
-- Node name is '~43~1'
-- Equation name is '~43~1', location is LC2_F33, type is buried.
-- synthesized logic cell
_LC2_F33 = LCELL( _EQ028);
_EQ028 = !c16
# !c17;
-- Node name is ':43'
-- Equation name is '_LC1_F33', type is buried
_LC1_F33 = LCELL( _EQ029);
_EQ029 = !c14 & !c15
# !c15 & _LC1_F52
# _LC2_F33;
-- Node name is ':60'
-- Equation name is '_LC1_F52', type is buried
_LC1_F52 = LCELL( _EQ030);
_EQ030 = !c13 & _LC4_C22
# !c12 & !c13
# !c11 & !c13;
-- Node name is ':75'
-- Equation name is '_LC4_C22', type is buried
_LC4_C22 = LCELL( _EQ031);
_EQ031 = !c10 & _LC5_C25
# !c9 & !c10
# !c8 & !c10;
-- Node name is ':90'
-- Equation name is '_LC5_C25', type is buried
_LC5_C25 = LCELL( _EQ032);
_EQ032 = !c6 & !c7
# !c5 & !c7;
-- Node name is ':320'
-- Equation name is '_LC5_F33', type is buried
_LC5_F33 = LCELL( _EQ033);
_EQ033 = !_LC2_F33 & _LC4_F52
# !_LC2_F33 & _LC8_F33
# c12 & !_LC2_F33;
-- Node name is '~328~1'
-- Equation name is '~328~1', location is LC8_F33, type is buried.
-- synthesized logic cell
_LC8_F33 = LCELL( _EQ034);
_EQ034 = c14
# c15
# c13;
-- Node name is ':345'
-- Equation name is '_LC4_F52', type is buried
_LC4_F52 = LCELL( _EQ035);
_EQ035 = c10 & c11 & _LC2_C22
# c9 & c10 & c11;
-- Node name is ':360'
-- Equation name is '_LC2_C22', type is buried
_LC2_C22 = LCELL( _EQ036);
_EQ036 = c6 & c8 & _LC2_C23
# c7 & c8;
-- Node name is '~378~1'
-- Equation name is '~378~1', location is LC8_C23, type is buried.
-- synthesized logic cell
_LC8_C23 = LCELL( _EQ037);
_EQ037 = c3
# c2
# c1;
-- Node name is ':378'
-- Equation name is '_LC2_C23', type is buried
_LC2_C23 = LCELL( _EQ038);
_EQ038 = _LC8_C23
# c4
# c5
# c0;
Project Information e:\cal\fp.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:05
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:06
Memory Allocated
-----------------
Peak memory allocated during compilation = 53,700K
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