fp.rpt
来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 788 行 · 第 1/3 页
RPT
788 行
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\cal\fp.rpt
fp
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
126 - - F -- OUTPUT 0 1 0 0 sec1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\cal\fp.rpt
fp
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 23 AND2 0 3 0 3 |LPM_ADD_SUB:167|addcore:adder|:119
- 1 - C 23 AND2 0 3 0 4 |LPM_ADD_SUB:167|addcore:adder|:127
- 3 - C 25 AND2 0 2 0 1 |LPM_ADD_SUB:167|addcore:adder|:131
- 5 - C 22 AND2 0 4 0 4 |LPM_ADD_SUB:167|addcore:adder|:139
- 8 - C 22 AND2 0 3 0 1 |LPM_ADD_SUB:167|addcore:adder|:147
- 1 - C 22 AND2 0 4 0 3 |LPM_ADD_SUB:167|addcore:adder|:151
- 8 - F 52 AND2 0 3 0 3 |LPM_ADD_SUB:167|addcore:adder|:159
- 2 - F 52 AND2 0 3 0 3 |LPM_ADD_SUB:167|addcore:adder|:167
- 6 - F 33 AND2 0 2 0 1 |LPM_ADD_SUB:167|addcore:adder|:171
- 7 - F 33 DFFE + 0 3 0 1 c17 (:3)
- 4 - F 33 DFFE + 0 3 0 2 c16 (:4)
- 3 - F 33 DFFE + 0 2 0 4 c15 (:5)
- 3 - F 52 DFFE + 0 3 0 3 c14 (:6)
- 6 - F 52 DFFE + 0 2 0 4 c13 (:7)
- 5 - F 52 DFFE + 0 3 0 3 c12 (:8)
- 7 - F 52 DFFE + 0 2 0 4 c11 (:9)
- 6 - C 22 DFFE + 0 2 0 3 c10 (:10)
- 3 - C 22 DFFE + 0 3 0 4 c9 (:11)
- 7 - C 22 DFFE + 0 2 0 5 c8 (:12)
- 8 - C 25 DFFE + 0 3 0 3 c7 (:13)
- 1 - C 25 DFFE + 0 3 0 4 c6 (:14)
- 6 - C 25 DFFE + 0 2 0 5 c5 (:15)
- 6 - C 23 DFFE + 0 3 0 2 c4 (:16)
- 7 - C 23 DFFE + 0 2 0 3 c3 (:17)
- 3 - C 23 DFFE + 0 3 0 2 c2 (:18)
- 4 - C 23 DFFE + 0 2 0 3 c1 (:19)
- 2 - C 25 DFFE + 0 1 0 4 c0 (:20)
- 2 - F 33 OR2 s 0 2 0 2 ~43~1
- 1 - F 33 OR2 0 4 0 18 :43
- 1 - F 52 OR2 0 4 0 1 :60
- 4 - C 22 OR2 0 4 0 1 :75
- 5 - C 25 OR2 0 3 0 1 :90
- 5 - F 33 OR2 0 4 1 0 :320
- 8 - F 33 OR2 s 0 3 0 1 ~328~1
- 4 - F 52 OR2 0 4 0 1 :345
- 2 - C 22 OR2 0 4 0 1 :360
- 8 - C 23 OR2 s 0 3 0 1 ~378~1
- 2 - C 23 OR2 0 4 0 1 :378
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\cal\fp.rpt
fp
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 7/208( 3%) 2/104( 1%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
D: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
E: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
F: 10/208( 4%) 0/104( 0%) 3/104( 2%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
G: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
H: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
I: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
J: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
K: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
L: 0/208( 0%) 0/104( 0%) 0/104( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
29: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
30: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
31: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
32: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
33: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
34: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
36: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
37: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
38: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
39: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
40: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
41: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
42: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
43: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
44: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
45: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
46: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
47: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
48: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
49: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
50: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
51: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
52: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\cal\fp.rpt
fp
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 18 clk
Device-Specific Information: e:\cal\fp.rpt
fp
** EQUATIONS **
clk : INPUT;
-- Node name is ':20' = 'c0'
-- Equation name is 'c0', location is LC2_C25, type is buried.
c0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !c0
# !_LC1_F33;
-- Node name is ':19' = 'c1'
-- Equation name is 'c1', location is LC4_C23, type is buried.
c1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = c0 & !c1 & _LC1_F33
# !c0 & c1 & _LC1_F33;
-- Node name is ':18' = 'c2'
-- Equation name is 'c2', location is LC3_C23, type is buried.
c2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !c0 & c2 & _LC1_F33
# !c1 & c2 & _LC1_F33
# c0 & c1 & !c2 & _LC1_F33;
-- Node name is ':17' = 'c3'
-- Equation name is 'c3', location is LC7_C23, type is buried.
c3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = c3 & _LC1_F33 & !_LC5_C23
# !c3 & _LC1_F33 & _LC5_C23;
-- Node name is ':16' = 'c4'
-- Equation name is 'c4', location is LC6_C23, type is buried.
c4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !c3 & c4 & _LC1_F33
# c4 & _LC1_F33 & !_LC5_C23
# c3 & !c4 & _LC1_F33 & _LC5_C23;
-- Node name is ':15' = 'c5'
-- Equation name is 'c5', location is LC6_C25, type is buried.
c5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = c5 & !_LC1_C23 & _LC1_F33
# !c5 & _LC1_C23 & _LC1_F33;
-- Node name is ':14' = 'c6'
-- Equation name is 'c6', location is LC1_C25, type is buried.
c6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !c5 & c6 & _LC1_F33
# c6 & !_LC1_C23 & _LC1_F33
# c5 & !c6 & _LC1_C23 & _LC1_F33;
-- Node name is ':13' = 'c7'
-- Equation name is 'c7', location is LC8_C25, type is buried.
c7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = c7 & _LC1_F33 & !_LC3_C25
# !c6 & c7 & _LC1_F33
# c6 & !c7 & _LC1_F33 & _LC3_C25;
-- Node name is ':12' = 'c8'
-- Equation name is 'c8', location is LC7_C22, type is buried.
c8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = c8 & _LC1_F33 & !_LC5_C22
# !c8 & _LC1_F33 & _LC5_C22;
-- Node name is ':11' = 'c9'
-- Equation name is 'c9', location is LC3_C22, type is buried.
c9 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !c8 & c9 & _LC1_F33
# c9 & _LC1_F33 & !_LC5_C22
# c8 & !c9 & _LC1_F33 & _LC5_C22;
-- Node name is ':10' = 'c10'
-- Equation name is 'c10', location is LC6_C22, type is buried.
c10 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = c10 & _LC1_F33 & !_LC8_C22
# !c10 & _LC1_F33 & _LC8_C22;
-- Node name is ':9' = 'c11'
-- Equation name is 'c11', location is LC7_F52, type is buried.
c11 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
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