bcdtob4.rpt

来自「ProtelDXp 实现计算器功能」· RPT 代码 · 共 687 行 · 第 1/3 页

CO9      =  _LC5_E52;

-- Node name is 'CO10' 
-- Equation name is 'CO10', type is output 
CO10     =  _LC2_E52;

-- Node name is 'CO11' 
-- Equation name is 'CO11', type is output 
CO11     =  _LC3_E52;

-- Node name is 'CO12' 
-- Equation name is 'CO12', type is output 
CO12     =  _LC1_E52;

-- Node name is 'CO13' 
-- Equation name is 'CO13', type is output 
CO13     =  _LC6_E52;

-- Node name is 'CO14' 
-- Equation name is 'CO14', type is output 
CO14     =  GND;

-- Node name is 'CO15' 
-- Equation name is 'CO15', type is output 
CO15     =  GND;

-- Node name is ':566' 
-- Equation name is '_LC6_E52', type is buried 
_LC6_E52 = LCELL( _EQ001);
  _EQ001 =  NUM0 & !NUM1 & !NUM2 &  NUM3;

-- Node name is ':674' 
-- Equation name is '_LC3_B6', type is buried 
!_LC3_B6 = _LC3_B6~NOT;
_LC3_B6~NOT = LCELL( _EQ002);
  _EQ002 =  NUM2
         #  NUM1
         #  NUM0
         #  NUM3;

-- Node name is '~778~1' 
-- Equation name is '~778~1', location is LC2_B6, type is buried.
-- synthesized logic cell 
!_LC2_B6 = _LC2_B6~NOT;
_LC2_B6~NOT = LCELL( _EQ003);
  _EQ003 =  NUM0 & !NUM1 & !NUM2 & !NUM3
         # !NUM0 &  NUM1 & !NUM2 & !NUM3;

-- Node name is ':778' 
-- Equation name is '_LC1_E52', type is buried 
_LC1_E52 = LCELL( _EQ004);
  _EQ004 =  NUM1 &  NUM2 & !NUM3
         #  NUM0 &  NUM2 & !NUM3
         # !NUM0 & !NUM1 & !NUM2 &  NUM3;

-- Node name is ':811' 
-- Equation name is '_LC3_E52', type is buried 
_LC3_E52 = LCELL( _EQ005);
  _EQ005 = !NUM0 & !NUM1 &  NUM2 & !NUM3
         #  NUM0 &  NUM1 & !NUM3
         # !NUM0 & !NUM1 & !NUM2 &  NUM3;

-- Node name is ':844' 
-- Equation name is '_LC2_E52', type is buried 
_LC2_E52 = LCELL( _EQ006);
  _EQ006 = !NUM0 &  NUM2 & !NUM3
         # !NUM0 & !NUM1 & !NUM2 &  NUM3
         # !NUM0 &  NUM1 & !NUM3;

-- Node name is '~877~1' 
-- Equation name is '~877~1', location is LC5_E52, type is buried.
-- synthesized logic cell 
_LC5_E52 = LCELL( _EQ007);
  _EQ007 =  NUM2 & !NUM3
         #  NUM1 & !NUM3
         #  NUM0 & !NUM3
         #  NUM0 & !NUM1 & !NUM2
         # !NUM1 & !NUM2 &  NUM3;

-- Node name is ':877' 
-- Equation name is '_LC4_E52', type is buried 
_LC4_E52 = LCELL( _EQ008);
  _EQ008 = !NUM0 &  NUM1 & !NUM3
         #  NUM0 & !NUM1 & !NUM3
         #  NUM0 & !NUM2 & !NUM3
         # !NUM0 &  NUM2 & !NUM3
         # !NUM1 & !NUM2 &  NUM3
         #  NUM1 &  NUM2 & !NUM3;

-- Node name is '~938~1' 
-- Equation name is '~938~1', location is LC7_B6, type is buried.
-- synthesized logic cell 
!_LC7_B6 = _LC7_B6~NOT;
_LC7_B6~NOT = LCELL( _EQ009);
  _EQ009 =  NUM3
         # !NUM1 & !NUM2
         # !NUM0 & !NUM2
         # !NUM0 &  NUM1
         #  NUM1 &  NUM2;

-- Node name is ':943' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = LCELL( _EQ010);
  _EQ010 = !_LC2_B6 & !_LC3_B6
         # !_LC3_B6 &  _LC7_B6;

-- Node name is ':956' 
-- Equation name is '_LC6_B6', type is buried 
_LC6_B6  = LCELL( _EQ011);
  _EQ011 = !NUM0 & !NUM1 & !NUM2 &  NUM3
         #  NUM1 &  NUM2 & !NUM3;

-- Node name is ':976' 
-- Equation name is '_LC8_B6', type is buried 
_LC8_B6  = LCELL( _EQ012);
  _EQ012 = !_LC2_B6 & !_LC3_B6
         # !_LC3_B6 &  _LC6_B6 & !_LC7_B6;

-- Node name is ':1009' 
-- Equation name is '_LC5_B6', type is buried 
_LC5_B6  = LCELL( _EQ013);
  _EQ013 =  NUM0 & !NUM2 & !NUM3
         #  NUM0 & !NUM1 & !NUM2
         # !NUM0 &  NUM2 & !NUM3;

-- Node name is ':1042' 
-- Equation name is '_LC7_E52', type is buried 
_LC7_E52 = LCELL( _EQ014);
  _EQ014 =  NUM1 & !NUM3;

-- Node name is ':1075' 
-- Equation name is '_LC4_B6', type is buried 
_LC4_B6  = LCELL( _EQ015);
  _EQ015 =  NUM0 & !NUM1 & !NUM2
         #  NUM0 & !NUM3;



Project Information                             e:\electron\bcdto2\bcdtob4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:04
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:05


Memory Allocated
-----------------

Peak memory allocated during compilation  = 53,165K