btobcd.vhd

来自「ProtelDXp 实现计算器功能」· VHDL 代码 · 共 219 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.all;
Entity btobcd is 
Port(							
			   CINA               				: in std_logic_vector(15 downto 0);
               BCD1,BCD2,BCD3,BCD4            : out std_logic_vector(3 downto 0)
     );
End btobcd;
Architecture A of BTOBCD is
Signal A1,A2,A3,A4,BCD,A5,A6,A7,A8,A9,A10,A11,A12,A13,A14,A15,B1,B2,B3,B4,B5,B6,B7,B8,B9,B10,B11,C1,C2,C3,C4,C5,C6,C7,C8:INTEGER RANGE -16 TO 100;  
signal  D1,D2,D3,D4,D5,E1,GW,SW,BW,QW,GJ,SJ,BJ,QJ,WW:INTEGER RANGE -16 TO 100;                                                                                                     
Begin
	process(CINA)
begin

	IF CINA(0)='1'THEN
		A1<=1;
    ELSE
		A1<=0;
    END IF;
    IF CINA(1)='1'THEN
		A2<=2;
	ELSE
		A2<=0;
    END IF;
    IF CINA(2)='1'THEN
		A3<=4;
	ELSE
		A3<=0;
    END IF;
    IF CINA(3)='1'THEN
		A4<=8;
	ELSE
		A4<=0;
    END IF;
    IF CINA(4)='1'THEN
		A5<=6;
		B1<=1;
	ELSE
		A5<=0;
		B1<=0;
   END IF;
   IF CINA(5)='1'THEN
		A6<=2;
		B2<=3;
	ELSE
		A6<=0;
		B2<=0;
    END IF;
    IF CINA(6)='1'THEN
		A7<=4;
		B3<=6;
	ELSE
		A7<=0;
		B3<=0;
    END IF;
    IF CINA(7)='1'THEN
		A8<=8;
		B4<=2;
		C1<=1;
	ELSE
		A8<=0;
		B4<=0;
		C1<=0;
    END IF;
    IF CINA(8)='1'THEN
		A9<=6;
		B5<=5;
		C2<=2;
	ELSE
		A9<=0;
		B5<=0;
		C2<=0;
    END IF;
    IF CINA(9)='1'THEN
		A10<=2;
		B6<=1;
		C3<=5;
	ELSE
		A10<=0;
		B6<=0;
		C3<=0;
    END IF;
    IF CINA(10)='1'THEN
		A11<=4;
		B7<=2;
		C4<=0;
		D1<=1;
	ELSE
		A11<=0;
		B7<=0;
		C4<=0;
		D1<=0;
    END IF;
    IF CINA(11)='1'THEN
		A12<=8;
		B8<=4;
		C5<=0;
		D2<=2;
	ELSE
		A12<=0;
		B8<=0;
		C5<=0;
		D2<=0;
   END IF;
   IF CINA(12)='1'THEN
		A13<=6;
		B9<=9;
		C6<=0;
		D3<=4;
   ELSE
		A13<=0;
		B9<=0;
		C6<=0;
		D3<=0;
   END IF;
   IF CINA(13)='1'THEN
		A14<=2;
		B10<=9;
		C7<=1;
		D4<=8;
	ELSE
		A14<=0;
		B10<=0;
		C7<=0;
		D4<=0;
    END IF;
    IF CINA(14)='1'THEN
		A15<=4;
		B11<=9;
		C8<=3;
		D5<=6;
		E1<=1;
	ELSE
		A15<=0;
		B11<=0;
		C8<=0;
		D5<=0;
		E1<=0;
    END IF;		
GW<=A1+A2+A3+A4+A5+A6+A7+A8+A9+A10+A11+A12+A13+A14+A15;
SW<=B1+B2+B3+B4+B5+B6+B7+B8+B9+B10+B11+GJ;
BW<=C1+C2+C3+C4+C5+C6+C7+C8+SJ;
QW<=D1+D2+D3+D4+D5+BJ;
WW<=E1+QJ;
IF GW>=60 THEN
	BCD1<=CONV_STD_LOGIC_VECTOR((GW-60),4);

	GJ<=6;
	ELSE IF GW>=50 THEN
							BCD1<=CONV_STD_LOGIC_VECTOR((GW-50),4);

								GJ<=5;
			ELSE IF GW>=40 THEN
						BCD1<=CONV_STD_LOGIC_VECTOR((GW-40),4);
	
							
							GW<=4;
					ELSE IF GW>=30 THEN
								BCD1<=CONV_STD_LOGIC_VECTOR((GW-30),4);
									GJ<=3;
							ELSE IF GW>=20 THEN
										BCD1<=CONV_STD_LOGIC_VECTOR((GW-20),4);
											GJ<=2;
									ELSE IF GW>=10 THEN
												BCD1<=CONV_STD_LOGIC_VECTOR((GW-10),4);
													GJ<=1;
										ELSE  
											BCD1<=CONV_STD_LOGIC_VECTOR(GW,4);
											GJ<=0;
										END IF;
								END IF;
						END IF;
				END IF;
		END IF;
END IF;
IF SW>=40 THEN
BCD2<=CONV_STD_LOGIC_VECTOR((SW-40),4);

	SJ<=4;
	ELSE IF SW>=30 THEN
							BCD2<=CONV_STD_LOGIC_VECTOR((SW-30),4);
								SJ<=3;
			ELSE IF SW>=20 THEN
								BCD2<=CONV_STD_LOGIC_VECTOR((SW-20),4);
								SW<=2;
					ELSE IF SW>=10 THEN
								BCD2<=CONV_STD_LOGIC_VECTOR((SW-10),4);
									SJ<=1;
							ELSE 
								BCD2<=CONV_STD_LOGIC_VECTOR(SW,4);
								SJ<=0;
								

						END IF;
				END IF;
		END IF;
END IF;
IF BW>=10 THEN
	BCD3<=CONV_STD_LOGIC_VECTOR((BW-10),4);
	BJ<=1;
	ELSE 								
		BCD3<=CONV_STD_LOGIC_VECTOR(BW,4);
		BJ<=0;
END IF;
IF QW>=10 THEN
		BCD4<=CONV_STD_LOGIC_VECTOR((QW-10),4);
		QJ<=1;
ELSE 
	BCD4<=CONV_STD_LOGIC_VECTOR(QW,4);
	QJ<=0;
END IF;
--A<=CONV_STD_LOGIC_VECTOR(WW,4);		
End PROCESS;
END;