dac.merge.rpt

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Partition Merge report for DAC
Sat Aug 08 18:18:11 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Partition Merge Summary
  3. Connections to In-System Debugging Instance "dds"
  4. Partition Merge Netlist Types Used
  5. Partition Merge Partition Statistics
  6. Partition Merge Partition Assignments
  7. Partition Merge Resource Usage Summary
  8. Partition Merge RAM Summary
  9. Partition Merge Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Partition Merge Summary                                                       ;
+------------------------------------+------------------------------------------+
; Partition Merge Status             ; Successful - Sat Aug 08 18:18:11 2009    ;
; Quartus II Version                 ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name                      ; DAC                                      ;
; Top-level Entity Name              ; DAC                                      ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 515                                      ;
;     Total combinational functions  ; 416                                      ;
;     Dedicated logic registers      ; 515                                      ;
; Total registers                    ; 515                                      ;
; Total pins                         ; 18 / 138 ( 13 % )                        ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 24,576 / 165,888 ( 15 % )                ;
; Embedded Multiplier 9-bit elements ; 0 / 36 ( 0 % )                           ;
; Total PLLs                         ; 0 / 2 ( 0 % )                            ;
+------------------------------------+------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Connections to In-System Debugging Instance "dds"                                                                                                                                                                                             ;
+----------------------------------------------------------------------------------+--------------+-----------+----------------+-------------------+----------------------------------------------------------------------------------+---------+
; Name                                                                             ; Type         ; Status    ; Partition Name ; Netlist Type Used ; Actual Connection                                                                ; Details ;
+----------------------------------------------------------------------------------+--------------+-----------+----------------+-------------------+----------------------------------------------------------------------------------+---------+
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10] ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10] ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10] ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10] ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11] ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11] ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11] ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11] ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]  ; N/A     ;
; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]  ; post-fitting ; connected ; Top            ; post-fit          ; ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]  ; N/A     ;
; clk_in                                                                           ; post-fitting ; connected ; Top            ; post-fit          ; clk_in                                                                           ; N/A     ;
+----------------------------------------------------------------------------------+--------------+-----------+----------------+-------------------+----------------------------------------------------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------+
; Partition Merge Netlist Types Used                                                                        ;
+----------------------+----------------+-------------------+------------------------+----------------------+
; Partition Name       ; Partition Type ; Netlist Type Used ; Netlist Type Requested ; Partition Contents   ;
+----------------------+----------------+-------------------+------------------------+----------------------+
; Top                  ; User-created   ; Post-Fit          ; Post-Fit               ;                      ;
; sld_hub:sld_hub_inst ; Auto-generated ; Source File       ; Source File            ; sld_hub:sld_hub_inst ;
; sld_signaltap:dds    ; Auto-generated ; Source File       ; Source File            ; sld_signaltap:dds    ;
+----------------------+----------------+-------------------+------------------------+----------------------+


+---------------------------------------------------------------------------------------------------------------+
; Partition Merge Partition Statistics                                                                          ;
+---------------------------------------------+---------------------+----------------------+--------------------+
; Statistic                                   ; Top                 ; sld_hub:sld_hub_inst ; sld_signaltap:dds  ;
+---------------------------------------------+---------------------+----------------------+--------------------+
; Estimated Total logic elements              ; 36 / 8256 ( < 1 % ) ; 104 / 8256 ( 1 % )   ; 412 / 8256 ( 4 % ) ;
;                                             ;                     ;                      ;                    ;
; Total combinational functions               ; 36                  ; 104                  ; 276                ;
; Logic element usage by number of LUT inputs ;                     ;                      ;                    ;
;     -- 4 input functions                    ; 5                   ; 40                   ; 91                 ;
;     -- 3 input functions                    ; 1                   ; 41                   ; 91                 ;
;     -- <=2 input functions                  ; 30                  ; 23                   ; 94                 ;
;                                             ;                     ;                      ;                    ;
; Logic elements by mode                      ;                     ;                      ;                    ;
;     -- normal mode                          ; 9                   ; 100                  ; 229                ;
;     -- arithmetic mode                      ; 27                  ; 4                    ; 47                 ;
;                                             ;                     ;                      ;                    ;
; Total registers                             ; 31                  ; 72                   ; 412                ;
;     -- Dedicated logic registers            ; 31 / 8256 ( < 1 % ) ; 72 / 8256 ( < 1 % )  ; 412 / 8256 ( 4 % ) ;