dac.fit.qmsg

DDS知识解析

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:02 " "Info: Fitter placement operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "7.371 ns register register " "Info: Estimated most critical path is register to register delay of 7.371 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|node_ena\[1\]~reg0 1 REG LAB_X17_Y12 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X17_Y12; Fanout = 6; REG Node = 'sld_hub:sld_hub_inst\|node_ena\[1\]~reg0'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|node_ena[1]~reg0 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 904 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.597 ns) + CELL(0.624 ns) 1.221 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sdr~14 2 COMB LAB_X18_Y12 23 " "Info: 2: + IC(0.597 ns) + CELL(0.624 ns) = 1.221 ns; Loc. = LAB_X18_Y12; Fanout = 23; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sdr~14'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.221 ns" { sld_hub:sld_hub_inst|node_ena[1]~reg0 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sdr~14 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_signaltap.vhd" 838 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.692 ns) + CELL(0.624 ns) 3.537 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|status_ram_shift_load~27 3 COMB LAB_X23_Y13 22 " "Info: 3: + IC(1.692 ns) + CELL(0.624 ns) = 3.537 ns; Loc. = LAB_X23_Y13; Fanout = 22; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|status_ram_shift_load~27'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.316 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sdr~14 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|status_ram_shift_load~27 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 613 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.322 ns) + CELL(0.206 ns) 5.065 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:status_data_shift_out\|_~1882 4 COMB LAB_X23_Y14 1 " "Info: 4: + IC(1.322 ns) + CELL(0.206 ns) = 5.065 ns; Loc. = LAB_X23_Y14; Fanout = 1; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:status_data_shift_out\|_~1882'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.528 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|status_ram_shift_load~27 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|_~1882 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 908 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.198 ns) + CELL(0.108 ns) 7.371 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:status_data_shift_out\|dffs\[0\] 5 REG LAB_X18_Y12 1 " "Info: 5: + IC(2.198 ns) + CELL(0.108 ns) = 7.371 ns; Loc. = LAB_X18_Y12; Fanout = 1; REG Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|lpm_shiftreg:status_data_shift_out\|dffs\[0\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.306 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|_~1882 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[0] } "NODE_NAME" } } { "LPM_SHIFTREG.tdf" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/LPM_SHIFTREG.tdf" 56 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.562 ns ( 21.19 % ) " "Info: Total cell delay = 1.562 ns ( 21.19 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.809 ns ( 78.81 % ) " "Info: Total interconnect delay = 5.809 ns ( 78.81 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.371 ns" { sld_hub:sld_hub_inst|node_ena[1]~reg0 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sdr~14 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|status_ram_shift_load~27 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|_~1882 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out|dffs[0] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_RCF_NUM_ROUTES_CONSTRAINED" "7.63 " "Info: Router is preserving 7.63 percent of routes from an earlier compile, a user specified Routing Constraints File, or internal routing requirements" {  } {  } 0 0 "Router is preserving %1!s! percent of routes from an earlier compile, a user specified Routing Constraints File, or internal routing requirements" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 " "Info: Average interconnect usage is 1% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "4 X23_Y10 X34_Y19 " "Info: Peak interconnect usage is 4% of the available device resources in the region that extends from location X23_Y10 to location X34_Y19" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "13 " "Warning: Found 13 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_clk 0 " "Info: Pin \"da_clk\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[11\] 0 " "Info: Pin \"da_data\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[10\] 0 " "Info: Pin \"da_data\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[9\] 0 " "Info: Pin \"da_data\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[8\] 0 " "Info: Pin \"da_data\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[7\] 0 " "Info: Pin \"da_data\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[6\] 0 " "Info: Pin \"da_data\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[5\] 0 " "Info: Pin \"da_data\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[4\] 0 " "Info: Pin \"da_data\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[3\] 0 " "Info: Pin \"da_data\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[2\] 0 " "Info: Pin \"da_data\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[1\] 0 " "Info: Pin \"da_data\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "da_data\[0\] 0 " "Info: Pin \"da_data\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/admin/Desktop/DDS/DAC/DAC.fit.smsg " "Info: Generated suppressed messages file C:/Users/admin/Desktop/DDS/DAC/DAC.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_USED" "1.3 2 2 " "Info: Parallel compilation was enabled and used an average of 1.3 processors and a maximum of 2 processors out of 2 processors allowed" { { "Info" "IQCU_PARALLEL_PER_PROCESSOR_TIME" "33 2 s " "Info: 33% of process time was spent using 2 processors" {  } {  } 0 0 "%1!i!%% of process time was spent using %2!i! processor%3!s!" 0 0 "" 0 0} { "Info" "IQCU_PARALLEL_PER_PROCESSOR_TIME" "67 1  " "Info: 67% of process time was spent using 1 processor" {  } {  } 0 0 "%1!i!%% of process time was spent using %2!i! processor%3!s!" 0 0 "" 0 0}  } {  } 0 0 "Parallel compilation was enabled and used an average of %1!s! processors and a maximum of %2!i! processors out of %3!i! processors allowed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 13 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 13 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "225 " "Info: Peak virtual memory: 225 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 08 18:18:22 2009 " "Info: Processing ended: Sat Aug 08 18:18:22 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Info: Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}