dac.map.qmsg

DDS知识解析

{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_rqf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/decode_rqf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_rqf " "Info: Found entity 1: decode_rqf" {  } { { "db/decode_rqf.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/decode_rqf.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_pbi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_pbi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_pbi " "Info: Found entity 1: cntr_pbi" {  } { { "db/cntr_pbi.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/cntr_pbi.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_8cc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_8cc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_8cc " "Info: Found entity 1: cmpr_8cc" {  } { { "db/cmpr_8cc.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/cmpr_8cc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_m4j.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_m4j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_m4j " "Info: Found entity 1: cntr_m4j" {  } { { "db/cntr_m4j.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/cntr_m4j.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_qbi.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_qbi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_qbi " "Info: Found entity 1: cntr_qbi" {  } { { "db/cntr_qbi.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/cntr_qbi.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_9cc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_9cc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_9cc " "Info: Found entity 1: cmpr_9cc" {  } { { "db/cmpr_9cc.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/cmpr_9cc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_gui.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_gui.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_gui " "Info: Found entity 1: cntr_gui" {  } { { "db/cntr_gui.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/cntr_gui.tdf" 30 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_5cc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_5cc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_5cc " "Info: Found entity 1: cmpr_5cc" {  } { { "db/cmpr_5cc.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/cmpr_5cc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_AE_SUCCESSFUL" "dds " "Info: Analysis and Synthesis generated SignalTap II or debug node instance \"dds\"" {  } {  } 0 0 "Analysis and Synthesis generated SignalTap II or debug node instance \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_QIC_SYNTHESIS_TOP_SEVERAL" "0 " "Info: 0 design partitions require synthesis" {  } {  } 0 0 "%1!d! design partitions require synthesis" 0 0 "" 0 0}
{ "Info" "ISGN_QIC_NO_SYNTHESIS_TOP_ONE" "" "Info: 1 design partition does not require synthesis" { { "Info" "ISGN_QIC_NO_SYNTHESIS_NO_CHANGE" "Top " "Info: Partition \"Top\" does not require synthesis because there were no relevant design changes" {  } {  } 0 0 "Partition \"%1!s!\" does not require synthesis because there were no relevant design changes" 0 0 "" 0 0}  } {  } 0 0 "1 design partition does not require synthesis" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_PARTITION" "sld_signaltap:dds " "Info: Starting High-Level Optimization for Partition sld_signaltap:dds" {  } {  } 0 0 "Starting High-Level Optimization for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_PARTITION" "sld_hub:sld_hub_inst " "Info: Starting High-Level Optimization for Partition sld_hub:sld_hub_inst" {  } {  } 0 0 "Starting High-Level Optimization for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_PARTITION" "sld_signaltap:dds " "Info: Starting High-Level Optimization for Partition sld_signaltap:dds" {  } {  } 0 0 "Starting High-Level Optimization for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_RTL_SYNTHESIZE_PARTITION" "sld_hub:sld_hub_inst " "Info: Starting High-Level Optimization for Partition sld_hub:sld_hub_inst" {  } {  } 0 0 "Starting High-Level Optimization for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "sld_signaltap:dds " "Info: Starting Logic Optimization and Technology Mapping for Partition sld_signaltap:dds" {  } {  } 0 0 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 88 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "651 " "Info: Implemented 651 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "81 " "Info: Implemented 81 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "34 " "Info: Implemented 34 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "524 " "Info: Implemented 524 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQSYN_SYNTHESIZE_PARTITION" "sld_hub:sld_hub_inst " "Info: Starting Logic Optimization and Technology Mapping for Partition sld_hub:sld_hub_inst" {  } {  } 0 0 "Starting Logic Optimization and Technology Mapping for Partition %1!s!" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0 "" 0 0}
{ "Info" "IOPT_MLS_DEV_CLRN_SETS_REGISTERS" "" "Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 0 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "171 " "Info: Implemented 171 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "18 " "Info: Implemented 18 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "36 " "Info: Implemented 36 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "117 " "Info: Implemented 117 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/admin/Desktop/DDS/DAC/DAC.map.smsg " "Info: Generated suppressed messages file C:/Users/admin/Desktop/DDS/DAC/DAC.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "224 " "Info: Peak virtual memory: 224 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 08 18:18:07 2009 " "Info: Processing ended: Sat Aug 08 18:18:07 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:10 " "Info: Total CPU time (on all processors): 00:00:10" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}