dac.hif

DDS知识解析

Version 8.1 Build 163 10/28/2008 SJ Full Version
11
945
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
DAC
# storage
db|DAC.(0).cnf
db|DAC.(0).cnf
# case_insensitive
# source_file
DAC.bdf
21e16aca37bc93d82f27a9c1da79a654
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence

# end
# entity
clk_div
# storage
db|DAC.(1).cnf
db|DAC.(1).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
clk_div.v
a95b09ee79a8f58d5fde7ab4cca7e
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
clk_div:inst
}
# macro_sequence

# end
# entity
ROM
# storage
db|DAC.(2).cnf
db|DAC.(2).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ROM.v
5642f728d4308971dd3e4547578da9fc
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
ROM:inst2
}
# macro_sequence

# end
# entity
altsyncram
# storage
db|DAC.(3).cnf
db|DAC.(3).cnf
# case_insensitive
# source_file
e:|program files|altera|81|quartus|libraries|megafunctions|altsyncram.tdf
428afb9bbf965842aa82c9b05526af
7
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
WIDTH_BYTEENA
1
PARAMETER_UNKNOWN
DEF
OPERATION_MODE
ROM
PARAMETER_UNKNOWN
USR
WIDTH_A
12
PARAMETER_SIGNED_DEC
USR
WIDTHAD_A
10
PARAMETER_SIGNED_DEC
USR
NUMWORDS_A
1024
PARAMETER_SIGNED_DEC
USR
OUTDATA_REG_A
CLOCK0
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
1
PARAMETER_UNKNOWN
DEF
WIDTHAD_B
1
PARAMETER_UNKNOWN
DEF
NUMWORDS_B
1
PARAMETER_UNKNOWN
DEF
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
DEF
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_SIGNED_DEC
USR
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
DEF
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_A
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_PORT_B
NEW_DATA_NO_NBE_READ
PARAMETER_UNKNOWN
DEF
INIT_FILE
sin1024.hex
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_A
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_CORE_B
USE_INPUT_CLKEN
PARAMETER_UNKNOWN
DEF
ENABLE_ECC
FALSE
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_ta31
PARAMETER_UNKNOWN
USR
}
# used_port {
q_a
-1
3
clock0
-1
3
address_a
-1
3
wren_b
-1
1
wren_a
-1
1
addressstall_b
-1
1
addressstall_a
-1
1
aclr1
-1
1
aclr0
-1
1
rden_b
-1
2
rden_a
-1
2
data_b
-1
2
data_a
-1
2
clocken3
-1
2
clocken2
-1
2
clocken1
-1
2
clocken0
-1
2
clock1
-1
2
byteena_b
-1
2
byteena_a
-1
2
address_b
-1
2
}
# include_file {
e:|program files|altera|81|quartus|libraries|megafunctions|altdpram.inc
99d442b5b66c88db4daf94d99c6e4e77
e:|program files|altera|81|quartus|libraries|megafunctions|altqpram.inc
74e08939f96a7ea8e7a4d59a5b01fe7
e:|program files|altera|81|quartus|libraries|megafunctions|lpm_mux.inc
c22bfd353214c01495b560fc34e47d79
e:|program files|altera|81|quartus|libraries|megafunctions|altram.inc
e66a83eccf6717bed97c99d891ad085
e:|program files|altera|81|quartus|libraries|megafunctions|altrom.inc
d4e3a69a331d3a99d3281790d99a1ebd
e:|program files|altera|81|quartus|libraries|megafunctions|a_rdenreg.inc
60d229340bc3c24acb0a137b4849830
e:|program files|altera|81|quartus|libraries|megafunctions|aglobal81.inc
ba79644cade9dcbd5df4af72a9b02986
e:|program files|altera|81|quartus|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
e:|program files|altera|81|quartus|libraries|megafunctions|stratix_ram_block.inc
2263a3bdfffeb150af977ee13902f70
}
# hierarchies {
ROM:inst2|altsyncram:altsyncram_component
}
# macro_sequence

# end
# entity
altsyncram_ta31
# storage
db|DAC.(4).cnf
db|DAC.(4).cnf
# case_insensitive
# source_file
db|altsyncram_ta31.tdf
95fc9ab3cb878c20a2547ea235c5a1c
7
# used_port {
q_a9
-1
3
q_a8
-1
3
q_a7
-1
3
q_a6
-1
3
q_a5
-1
3
q_a4
-1
3
q_a3
-1
3
q_a2
-1
3
q_a11
-1
3
q_a10
-1
3
q_a1
-1
3
q_a0
-1
3
clock0
-1
3
address_a9
-1
3
address_a8
-1
3
address_a7
-1
3
address_a6
-1
3
address_a5
-1
3
address_a4
-1
3
address_a3
-1
3
address_a2
-1
3
address_a1
-1
3
address_a0
-1
3
}
# memory_file {
sin1024.hex
52485b9ffc8acc551139e85196bd5f27
}
# hierarchies {
ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated
}
# macro_sequence

# end
# entity
COUNTER
# storage
db|DAC.(5).cnf
db|DAC.(5).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
COUNTER.v
4bd6148bd022fa1bf838c2c6bf438c0
8
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
VERILOG_CONSTANT_LOOP_LIMIT
5000
VERILOG_NON_CONSTANT_LOOP_LIMIT
250
}
# hierarchies {
COUNTER:inst4
}
# macro_sequence

# end
# entity
lpm_add_sub
# storage
db|DAC.(6).cnf
db|DAC.(6).cnf
# case_insensitive
# source_file
e:|program files|altera|81|quartus|libraries|megafunctions|lpm_add_sub.tdf
1c1195a367bf9152c0cd4ed197d726c2
7
# user_parameter {
LPM_WIDTH
24
PARAMETER_SIGNED_DEC
USR
LPM_REPRESENTATION
UNSIGNED
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
YES
PARAMETER_UNKNOWN
USR
LPM_PIPELINE
1
PARAMETER_SIGNED_DEC
USR
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
USE_WYS
OFF
PARAMETER_UNKNOWN
DEF
STYLE
FAST
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
add_sub_6nj
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
result
-1
3
datab
-1
3
dataa
-1
3
clock
-1
3
}
# include_file {
e:|program files|altera|81|quartus|libraries|megafunctions|alt_mercury_add_sub.inc
ae39f15ed67cc9a095d29f68f6ad0f8
e:|program files|altera|81|quartus|libraries|megafunctions|bypassff.inc
8e8df160d449a63ec15dc86ecf2b373f
e:|program files|altera|81|quartus|libraries|megafunctions|altshift.inc
70fa13aee7d6d160ef20b2de32813a
e:|program files|altera|81|quartus|libraries|megafunctions|aglobal81.inc
ba79644cade9dcbd5df4af72a9b02986
e:|program files|altera|81|quartus|libraries|megafunctions|alt_stratix_add_sub.inc
c08f604aefba5b4f1f554e565113c6
e:|program files|altera|81|quartus|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
e:|program files|altera|81|quartus|libraries|megafunctions|look_add.inc
ab9f577d30c5ef3166fab6c1c32c4a
}
# hierarchies {
COUNTER:inst4|lpm_add_sub:lpm_add_sub_component
}
# macro_sequence

# end
# entity
add_sub_6nj
# storage
db|DAC.(7).cnf
db|DAC.(7).cnf
# case_insensitive
# source_file
db|add_sub_6nj.tdf
634e4a08a51de961c94214ffaa0a0
7
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result23
-1
3
result22
-1
3
result21
-1
3
result20
-1
3
result2
-1
3
result19
-1
3
result18
-1
3
result17
-1
3
result16
-1
3
result15
-1
3
result14
-1
3
result13
-1
3
result12
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
datab9
-1
3
datab8
-1
3
datab7
-1
3
datab6
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab23
-1
3
datab22
-1
3
datab21
-1
3
datab20
-1
3
datab2
-1
3
datab19
-1
3
datab18
-1
3
datab17
-1
3
datab16
-1
3
datab15
-1
3
datab14
-1
3
datab13
-1
3
datab12
-1
3
datab11
-1
3
datab10
-1
3
datab1
-1
3
datab0
-1
3
dataa9
-1
3
dataa8
-1
3
dataa7
-1
3
dataa6
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa23
-1
3
dataa22
-1
3
dataa21
-1
3
dataa20
-1
3
dataa2
-1
3
dataa19
-1
3
dataa18
-1
3
dataa17
-1
3
dataa16
-1
3
dataa15
-1
3
dataa14
-1
3
dataa13
-1
3
dataa12
-1
3
dataa11
-1
3
dataa10
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
}
# hierarchies {
COUNTER:inst4|lpm_add_sub:lpm_add_sub_component|add_sub_6nj:auto_generated
}
# macro_sequence

# end
# entity
sld_signaltap
# storage
db|DAC.(8).cnf
db|DAC.(8).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_insensitive
# source_file
e:|program files|altera|81|quartus|libraries|megafunctions|sld_signaltap.vhd
1acad66a26c948ca4cfdc53c9dc26d
5
# internal_option {
IP_SHOW_ELABORATION_MESSAGES
OFF
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
}
# user_parameter {
lpm_type
sld_signaltap
PARAMETER_STRING
DEF
sld_node_info
805334528
PARAMETER_UNKNOWN
USR
SLD_IP_VERSION
6
PARAMETER_SIGNED_DEC
DEF
SLD_IP_MINOR_VERSION
0
PARAMETER_SIGNED_DEC
DEF
SLD_COMMON_IP_VERSION
0
PARAMETER_SIGNED_DEC
DEF
sld_data_bits
12
PARAMETER_UNKNOWN
USR
sld_trigger_bits
12
PARAMETER_UNKNOWN
USR
SLD_NODE_CRC_BITS
32
PARAMETER_SIGNED_DEC
DEF
sld_node_crc_hiword
61347
PARAMETER_UNKNOWN
USR
sld_node_crc_loword
39194
PARAMETER_UNKNOWN
USR
SLD_INCREMENTAL_ROUTING
0
PARAMETER_SIGNED_DEC
DEF
sld_sample_depth
1024
PARAMETER_UNKNOWN
USR
sld_segment_size
1024
PARAMETER_UNKNOWN
USR
SLD_RAM_BLOCK_TYPE
AUTO
PARAMETER_STRING
DEF
sld_state_bits
11
PARAMETER_UNKNOWN
USR
sld_buffer_full_stop
1
PARAMETER_UNKNOWN
USR
SLD_MEM_ADDRESS_BITS
7
PARAMETER_SIGNED_DEC
DEF
SLD_DATA_BIT_CNTR_BITS
4
PARAMETER_SIGNED_DEC
DEF
sld_trigger_level
1
PARAMETER_UNKNOWN
USR
sld_trigger_in_enabled
0
PARAMETER_UNKNOWN
USR
sld_advanced_trigger_entity
basic,1,
PARAMETER_UNKNOWN
USR
sld_trigger_level_pipeline
1
PARAMETER_UNKNOWN
USR
sld_enable_advanced_trigger
0
PARAMETER_UNKNOWN
USR
SLD_ADVANCED_TRIGGER_1
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_2
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_3
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_4
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_5
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_6
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_7
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_8
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_9
NONE
PARAMETER_STRING
DEF
SLD_ADVANCED_TRIGGER_10
NONE
PARAMETER_STRING
DEF
sld_inversion_mask_length
60
PARAMETER_UNKNOWN
USR
sld_inversion_mask
000000000000000000000000000000000000000000000000000000000000
PARAMETER_UNKNOWN
USR
sld_power_up_trigger
0
PARAMETER_UNKNOWN
USR
SLD_STATE_FLOW_MGR_ENTITY
state_flow_mgr_entity.vhd
PARAMETER_STRING
DEF
sld_state_flow_use_generated
0
PARAMETER_UNKNOWN
USR