prev_cmp_dac.map.qmsg

DDS知识解析

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 08 18:14:00 2009 " "Info: Processing started: Sat Aug 08 18:14:00 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DAC -c DAC " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DAC -c DAC" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "clk_div.v(17) " "Warning (10268): Verilog HDL information at clk_div.v(17): always construct contains both blocking and non-blocking assignments" {  } { { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clk_div.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clk_div.v" { { "Info" "ISGN_ENTITY_NAME" "1 clk_div " "Info: Found entity 1: clk_div" {  } { { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 9 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADDR_COUNTER.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ADDR_COUNTER.v" { { "Info" "ISGN_ENTITY_NAME" "1 ADDR_COUNTER " "Info: Found entity 1: ADDR_COUNTER" {  } { { "ADDR_COUNTER.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/ADDR_COUNTER.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ROM.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ROM.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROM " "Info: Found entity 1: ROM" {  } { { "ROM.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/ROM.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DAC.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DAC.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DAC " "Info: Found entity 1: DAC" {  } { { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "COUNTER.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file COUNTER.v" { { "Info" "ISGN_ENTITY_NAME" "1 COUNTER " "Info: Found entity 1: COUNTER" {  } { { "COUNTER.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/COUNTER.v" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DAC " "Info: Elaborating entity \"DAC\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clk_div clk_div:inst " "Info: Elaborating entity \"clk_div\" for hierarchy \"clk_div:inst\"" {  } { { "DAC.bdf" "inst" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 128 120 240 224 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 12 clk_div.v(26) " "Warning (10230): Verilog HDL assignment warning at clk_div.v(26): truncated value with size 32 to match size of target (12)" {  } { { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 26 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ROM ROM:inst2 " "Info: Elaborating entity \"ROM\" for hierarchy \"ROM:inst2\"" {  } { { "DAC.bdf" "inst2" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 48 584 800 184 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ROM:inst2\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"ROM:inst2\|altsyncram:altsyncram_component\"" {  } { { "ROM.v" "altsyncram_component" { Text "C:/Users/admin/Desktop/DDS/DAC/ROM.v" 74 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ROM:inst2\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"ROM:inst2\|altsyncram:altsyncram_component\"" {  } { { "ROM.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/ROM.v" 74 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ROM:inst2\|altsyncram:altsyncram_component " "Info: Instantiated megafunction \"ROM:inst2\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Info: Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "init_file sin1024.hex " "Info: Parameter \"init_file\" = \"sin1024.hex\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Cyclone " "Info: Parameter \"intended_device_family\" = \"Cyclone\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ENABLE_RUNTIME_MOD=NO " "Info: Parameter \"lpm_hint\" = \"ENABLE_RUNTIME_MOD=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Info: Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 1024 " "Info: Parameter \"numwords_a\" = \"1024\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode ROM " "Info: Parameter \"operation_mode\" = \"ROM\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_a NONE " "Info: Parameter \"outdata_aclr_a\" = \"NONE\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_a CLOCK0 " "Info: Parameter \"outdata_reg_a\" = \"CLOCK0\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 10 " "Info: Parameter \"widthad_a\" = \"10\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 12 " "Info: Parameter \"width_a\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Info: Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "ROM.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/ROM.v" 74 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_ta31.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_ta31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_ta31 " "Info: Found entity 1: altsyncram_ta31" {  } { { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_ta31 ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated " "Info: Elaborating entity \"altsyncram_ta31\" for hierarchy \"ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "COUNTER COUNTER:inst4 " "Info: Elaborating entity \"COUNTER\" for hierarchy \"COUNTER:inst4\"" {  } { { "DAC.bdf" "inst4" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 24 296 456 120 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_add_sub COUNTER:inst4\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborating entity \"lpm_add_sub\" for hierarchy \"COUNTER:inst4\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "COUNTER.v" "lpm_add_sub_component" { Text "C:/Users/admin/Desktop/DDS/DAC/COUNTER.v" 66 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "COUNTER:inst4\|lpm_add_sub:lpm_add_sub_component " "Info: Elaborated megafunction instantiation \"COUNTER:inst4\|lpm_add_sub:lpm_add_sub_component\"" {  } { { "COUNTER.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/COUNTER.v" 66 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 0}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "COUNTER:inst4\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"COUNTER:inst4\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_direction ADD " "Info: Parameter \"lpm_direction\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_hint ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO " "Info: Parameter \"lpm_hint\" = \"ONE_INPUT_IS_CONSTANT=YES,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_pipeline 1 " "Info: Parameter \"lpm_pipeline\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_representation UNSIGNED " "Info: Parameter \"lpm_representation\" = \"UNSIGNED\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type LPM_ADD_SUB " "Info: Parameter \"lpm_type\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 24 " "Info: Parameter \"lpm_width\" = \"24\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "" 0 0}  } { { "COUNTER.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/COUNTER.v" 66 0 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_6nj.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_6nj.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_6nj " "Info: Found entity 1: add_sub_6nj" {  } { { "db/add_sub_6nj.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/add_sub_6nj.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "add_sub_6nj COUNTER:inst4\|lpm_add_sub:lpm_add_sub_component\|add_sub_6nj:auto_generated " "Info: Elaborating entity \"add_sub_6nj\" for hierarchy \"COUNTER:inst4\|lpm_add_sub:lpm_add_sub_component\|add_sub_6nj:auto_generated\"" {  } { { "lpm_add_sub.tdf" "auto_generated" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/lpm_add_sub.tdf" 119 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/admin/Desktop/DDS/DAC/DAC.map.smsg " "Info: Generated suppressed messages file C:/Users/admin/Desktop/DDS/DAC/DAC.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "ICUT_CUT_TM_SUMMARY" "61 " "Info: Implemented 61 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_OPINS" "13 " "Info: Implemented 13 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_LCELLS" "35 " "Info: Implemented 35 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 0} { "Info" "ICUT_CUT_TM_RAMS" "12 " "Info: Implemented 12 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0 "" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "200 " "Info: Peak virtual memory: 200 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 08 18:14:06 2009 " "Info: Processing ended: Sat Aug 08 18:14:06 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}