prev_cmp_dac.qmsg

DDS知识解析

{ "Info" "IQCU_PARALLEL_USED" "1.0 2 2 " "Info: Parallel compilation was enabled and used an average of 1.0 processors and a maximum of 2 processors out of 2 processors allowed" { { "Info" "IQCU_PARALLEL_INSIGNIFICANT_TIME" "" "Info: Less than 1% of process time was spent using more than one processor" {  } {  } 0 0 "Less than 1%% of process time was spent using more than one processor" 0 0 "" 0 0}  } {  } 0 0 "Parallel compilation was enabled and used an average of %1!s! processors and a maximum of %2!i! processors out of %3!i! processors allowed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 2 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "221 " "Info: Peak virtual memory: 221 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 08 18:14:17 2009 " "Info: Processing ended: Sat Aug 08 18:14:17 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 08 18:14:20 2009 " "Info: Processing started: Sat Aug 08 18:14:20 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off DAC -c DAC " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off DAC -c DAC" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 0}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "186 " "Info: Peak virtual memory: 186 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 08 18:14:22 2009 " "Info: Processing ended: Sat Aug 08 18:14:22 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.1 Build 163 10/28/2008 SJ Full Version " "Info: Version 8.1 Build 163 10/28/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Aug 08 18:14:23 2009 " "Info: Processing started: Sat Aug 08 18:14:23 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off DAC -c DAC --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off DAC -c DAC --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" {  } {  } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_in " "Info: Assuming node \"clk_in\" is an undefined clock" {  } { { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } } { "e:/program files/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_in" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "1 " "Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk_div:inst\|clk_reg " "Info: Detected ripple clock \"clk_div:inst\|clk_reg\" as buffer" {  } { { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } } { "e:/program files/altera/81/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/program files/altera/81/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_div:inst\|clk_reg" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_in memory memory ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0 ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\] 180.05 MHz Internal " "Info: Clock \"clk_in\" Internal fmax is restricted to 180.05 MHz between source memory \"ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0\" and destination memory \"ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.777 ns 2.777 ns 5.554 ns " "Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0 1 MEM M4K_X11_Y18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y18; Fanout = 4; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 194 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\] 2 MEM M4K_X11_Y18 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X11_Y18; Fanout = 1; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] {} } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 5.119 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk_in\" to destination memory is 5.119 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_in 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk_in'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns clk_div:inst\|clk_reg 2 REG LCFF_X1_Y9_N17 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y9_N17; Fanout = 3; REG Node = 'clk_div:inst\|clk_reg'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk_in clk_div:inst|clk_reg } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.000 ns) 3.449 ns clk_div:inst\|clk_reg~clkctrl 3 COMB CLKCTRL_G1 60 " "Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 3.449 ns; Loc. = CLKCTRL_G1; Fanout = 60; COMB Node = 'clk_div:inst\|clk_reg~clkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.815 ns) 5.119 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\] 4 MEM M4K_X11_Y18 1 " "Info: 4: + IC(0.855 ns) + CELL(0.815 ns) = 5.119 ns; Loc. = M4K_X11_Y18; Fanout = 1; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.670 ns" { clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.925 ns ( 57.14 % ) " "Info: Total cell delay = 2.925 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.194 ns ( 42.86 % ) " "Info: Total interconnect delay = 2.194 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.119 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.119 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 5.139 ns - Longest memory " "Info: - Longest clock path from clock \"clk_in\" to source memory is 5.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_in 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk_in'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns clk_div:inst\|clk_reg 2 REG LCFF_X1_Y9_N17 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y9_N17; Fanout = 3; REG Node = 'clk_div:inst\|clk_reg'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk_in clk_div:inst|clk_reg } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.000 ns) 3.449 ns clk_div:inst\|clk_reg~clkctrl 3 COMB CLKCTRL_G1 60 " "Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 3.449 ns; Loc. = CLKCTRL_G1; Fanout =