dac.tan.qmsg

DDS知识解析

{ "Info" "ITDB_TSU_RESULT" "sld_hub:sld_hub_inst\|hub_mode_reg\[1\] altera_internal_jtag~TMSUTAP altera_internal_jtag~TCKUTAP 2.406 ns register " "Info: tsu for register \"sld_hub:sld_hub_inst\|hub_mode_reg\[1\]\" (data pin = \"altera_internal_jtag~TMSUTAP\", clock pin = \"altera_internal_jtag~TCKUTAP\") is 2.406 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.829 ns + Longest pin register " "Info: + Longest pin to register delay is 7.829 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TMSUTAP 1 PIN JTAG_X1_Y10_N0 23 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 23; PIN Node = 'altera_internal_jtag~TMSUTAP'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TMSUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.743 ns) + CELL(0.650 ns) 4.393 ns sld_hub:sld_hub_inst\|hub_mode_reg\[1\]~461 2 COMB LCCOMB_X17_Y12_N22 3 " "Info: 2: + IC(3.743 ns) + CELL(0.650 ns) = 4.393 ns; Loc. = LCCOMB_X17_Y12_N22; Fanout = 3; COMB Node = 'sld_hub:sld_hub_inst\|hub_mode_reg\[1\]~461'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.393 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|hub_mode_reg[1]~461 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 298 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.257 ns) + CELL(0.370 ns) 6.020 ns sld_hub:sld_hub_inst\|hub_mode_reg\[1\]~462 3 COMB LCCOMB_X17_Y13_N8 1 " "Info: 3: + IC(1.257 ns) + CELL(0.370 ns) = 6.020 ns; Loc. = LCCOMB_X17_Y13_N8; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_mode_reg\[1\]~462'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.627 ns" { sld_hub:sld_hub_inst|hub_mode_reg[1]~461 sld_hub:sld_hub_inst|hub_mode_reg[1]~462 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 298 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.077 ns) + CELL(0.624 ns) 7.721 ns sld_hub:sld_hub_inst\|hub_mode_reg\[1\]~464 4 COMB LCCOMB_X19_Y13_N24 1 " "Info: 4: + IC(1.077 ns) + CELL(0.624 ns) = 7.721 ns; Loc. = LCCOMB_X19_Y13_N24; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_mode_reg\[1\]~464'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.701 ns" { sld_hub:sld_hub_inst|hub_mode_reg[1]~462 sld_hub:sld_hub_inst|hub_mode_reg[1]~464 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 298 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 7.829 ns sld_hub:sld_hub_inst\|hub_mode_reg\[1\] 5 REG LCFF_X19_Y13_N25 8 " "Info: 5: + IC(0.000 ns) + CELL(0.108 ns) = 7.829 ns; Loc. = LCFF_X19_Y13_N25; Fanout = 8; REG Node = 'sld_hub:sld_hub_inst\|hub_mode_reg\[1\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|hub_mode_reg[1]~464 sld_hub:sld_hub_inst|hub_mode_reg[1] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 298 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.752 ns ( 22.38 % ) " "Info: Total cell delay = 1.752 ns ( 22.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.077 ns ( 77.62 % ) " "Info: Total interconnect delay = 6.077 ns ( 77.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.829 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|hub_mode_reg[1]~461 sld_hub:sld_hub_inst|hub_mode_reg[1]~462 sld_hub:sld_hub_inst|hub_mode_reg[1]~464 sld_hub:sld_hub_inst|hub_mode_reg[1] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "7.829 ns" { altera_internal_jtag~TMSUTAP {} sld_hub:sld_hub_inst|hub_mode_reg[1]~461 {} sld_hub:sld_hub_inst|hub_mode_reg[1]~462 {} sld_hub:sld_hub_inst|hub_mode_reg[1]~464 {} sld_hub:sld_hub_inst|hub_mode_reg[1] {} } { 0.000ns 3.743ns 1.257ns 1.077ns 0.000ns } { 0.000ns 0.650ns 0.370ns 0.624ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 298 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.383 ns - Shortest register " "Info: - Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.825 ns) + CELL(0.000 ns) 3.825 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 285 " "Info: 2: + IC(3.825 ns) + CELL(0.000 ns) = 3.825 ns; Loc. = CLKCTRL_G3; Fanout = 285; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.825 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.666 ns) 5.383 ns sld_hub:sld_hub_inst\|hub_mode_reg\[1\] 3 REG LCFF_X19_Y13_N25 8 " "Info: 3: + IC(0.892 ns) + CELL(0.666 ns) = 5.383 ns; Loc. = LCFF_X19_Y13_N25; Fanout = 8; REG Node = 'sld_hub:sld_hub_inst\|hub_mode_reg\[1\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.558 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_mode_reg[1] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 298 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.37 % ) " "Info: Total cell delay = 0.666 ns ( 12.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.717 ns ( 87.63 % ) " "Info: Total interconnect delay = 4.717 ns ( 87.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.383 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_mode_reg[1] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.383 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_mode_reg[1] {} } { 0.000ns 3.825ns 0.892ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "7.829 ns" { altera_internal_jtag~TMSUTAP sld_hub:sld_hub_inst|hub_mode_reg[1]~461 sld_hub:sld_hub_inst|hub_mode_reg[1]~462 sld_hub:sld_hub_inst|hub_mode_reg[1]~464 sld_hub:sld_hub_inst|hub_mode_reg[1] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "7.829 ns" { altera_internal_jtag~TMSUTAP {} sld_hub:sld_hub_inst|hub_mode_reg[1]~461 {} sld_hub:sld_hub_inst|hub_mode_reg[1]~462 {} sld_hub:sld_hub_inst|hub_mode_reg[1]~464 {} sld_hub:sld_hub_inst|hub_mode_reg[1] {} } { 0.000ns 3.743ns 1.257ns 1.077ns 0.000ns } { 0.000ns 0.650ns 0.370ns 0.624ns 0.108ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.383 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|hub_mode_reg[1] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.383 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|hub_mode_reg[1] {} } { 0.000ns 3.825ns 0.892ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in da_data\[0\] ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\] 10.372 ns memory " "Info: tco from clock \"clk_in\" to destination pin \"da_data\[0\]\" through memory \"ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\]\" is 10.372 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 5.117 ns + Longest memory " "Info: + Longest clock path from clock \"clk_in\" to source memory is 5.117 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_in 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk_in'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns clk_div:inst\|clk_reg 2 REG LCFF_X1_Y9_N17 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y9_N17; Fanout = 3; REG Node = 'clk_div:inst\|clk_reg'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk_in clk_div:inst|clk_reg } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.000 ns) 3.449 ns clk_div:inst\|clk_reg~clkctrl 3 COMB CLKCTRL_G1 60 " "Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 3.449 ns; Loc. = CLKCTRL_G1; Fanout = 60; COMB Node = 'clk_div:inst\|clk_reg~clkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.815 ns) 5.117 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\] 4 MEM M4K_X11_Y16 3 " "Info: 4: + IC(0.853 ns) + CELL(0.815 ns) = 5.117 ns; Loc. = M4K_X11_Y16; Fanout = 3; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.668 ns" { clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.925 ns ( 57.16 % ) " "Info: Total cell delay = 2.925 ns ( 57.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.192 ns ( 42.84 % ) " "Info: Total interconnect delay = 2.192 ns ( 42.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.117 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.117 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.853ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.995 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.995 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\] 1 MEM M4K_X11_Y16 3 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y16; Fanout = 3; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsy