dac.tan.qmsg

DDS知识解析

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\] register sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\] 150.97 MHz 6.624 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 150.97 MHz between source register \"sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\]\" and destination register \"sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\]\" (period= 6.624 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.368 ns + Longest register register " "Info: + Longest register to register delay is 6.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\] 1 REG LCFF_X29_Y12_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X29_Y12_N3; Fanout = 4; REG Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 93 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.135 ns) + CELL(0.646 ns) 1.781 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~106 2 COMB LCCOMB_X31_Y12_N4 1 " "Info: 2: + IC(1.135 ns) + CELL(0.646 ns) = 1.781 ns; Loc. = LCCOMB_X31_Y12_N4; Fanout = 1; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~106'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.781 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~106 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.373 ns) + CELL(0.370 ns) 2.524 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~110 3 COMB LCCOMB_X31_Y12_N18 1 " "Info: 3: + IC(0.373 ns) + CELL(0.370 ns) = 2.524 ns; Loc. = LCCOMB_X31_Y12_N18; Fanout = 1; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~110'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.743 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~106 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~110 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.365 ns) + CELL(0.206 ns) 3.095 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~112 4 COMB LCCOMB_X31_Y12_N28 17 " "Info: 4: + IC(0.365 ns) + CELL(0.206 ns) = 3.095 ns; Loc. = LCCOMB_X31_Y12_N28; Fanout = 17; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|Equal1~112'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.571 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~110 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~112 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.416 ns) + CELL(0.206 ns) 3.717 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|segment_shift_var~3 5 COMB LCCOMB_X31_Y12_N10 11 " "Info: 5: + IC(0.416 ns) + CELL(0.206 ns) = 3.717 ns; Loc. = LCCOMB_X31_Y12_N10; Fanout = 11; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|segment_shift_var~3'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.622 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~112 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~3 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 350 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.460 ns) + CELL(0.202 ns) 5.379 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count~127 6 COMB LCCOMB_X30_Y13_N2 3 " "Info: 6: + IC(1.460 ns) + CELL(0.202 ns) = 5.379 ns; Loc. = LCCOMB_X30_Y13_N2; Fanout = 3; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|offset_count~127'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.662 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~3 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~127 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 338 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.206 ns) 6.260 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\]~feeder 7 COMB LCCOMB_X29_Y13_N24 1 " "Info: 7: + IC(0.675 ns) + CELL(0.206 ns) = 6.260 ns; Loc. = LCCOMB_X29_Y13_N24; Fanout = 1; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\]~feeder'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.881 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~127 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9]~feeder } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 350 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 6.368 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\] 8 REG LCFF_X29_Y13_N25 1 " "Info: 8: + IC(0.000 ns) + CELL(0.108 ns) = 6.368 ns; Loc. = LCFF_X29_Y13_N25; Fanout = 1; REG Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9]~feeder sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 350 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.944 ns ( 30.53 % ) " "Info: Total cell delay = 1.944 ns ( 30.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.424 ns ( 69.47 % ) " "Info: Total interconnect delay = 4.424 ns ( 69.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.368 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~106 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~110 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~112 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~3 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~127 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9]~feeder sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "6.368 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~106 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~110 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~112 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~3 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~127 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9]~feeder {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] {} } { 0.000ns 1.135ns 0.373ns 0.365ns 0.416ns 1.460ns 0.675ns 0.000ns } { 0.000ns 0.646ns 0.370ns 0.206ns 0.206ns 0.202ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.008 ns - Smallest " "Info: - Smallest clock skew is 0.008 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 2.859 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 2.859 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_in 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk_in'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_in~clkctrl 2 COMB CLKCTRL_G2 297 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 297; COMB Node = 'clk_in~clkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.914 ns) + CELL(0.666 ns) 2.859 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\] 3 REG LCFF_X29_Y13_N25 1 " "Info: 3: + IC(0.914 ns) + CELL(0.666 ns) = 2.859 ns; Loc. = LCFF_X29_Y13_N25; Fanout = 1; REG Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[9\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.580 ns" { clk_in~clkctrl sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 350 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.17 % ) " "Info: Total cell delay = 1.806 ns ( 63.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.053 ns ( 36.83 % ) " "Info: Total interconnect delay = 1.053 ns ( 36.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.859 ns" { clk_in clk_in~clkctrl sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "2.859 ns" { clk_in {} clk_in~combout {} clk_in~clkctrl {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] {} } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 2.851 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 2.851 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_in 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk_in'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.139 ns) + CELL(0.000 ns) 1.279 ns clk_in~clkctrl 2 COMB CLKCTRL_G2 297 " "Info: 2: + IC(0.139 ns) + CELL(0.000 ns) = 1.279 ns; Loc. = CLKCTRL_G2; Fanout = 297; COMB Node = 'clk_in~clkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.139 ns" { clk_in clk_in~clkctrl } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.906 ns) + CELL(0.666 ns) 2.851 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\] 3 REG LCFF_X29_Y12_N3 4 " "Info: 3: + IC(0.906 ns) + CELL(0.666 ns) = 2.851 ns; Loc. = LCFF_X29_Y12_N3; Fanout = 4; REG Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|counter\[6\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.572 ns" { clk_in~clkctrl sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 93 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.806 ns ( 63.35 % ) " "Info: Total cell delay = 1.806 ns ( 63.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.045 ns ( 36.65 % ) " "Info: Total interconnect delay = 1.045 ns ( 36.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.851 ns" { clk_in clk_in~clkctrl sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "2.851 ns" { clk_in {} clk_in~combout {} clk_in~clkctrl {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.859 ns" { clk_in clk_in~clkctrl sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "2.859 ns" { clk_in {} clk_in~combout {} clk_in~clkctrl {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] {} } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.851 ns" { clk_in clk_in~clkctrl sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "2.851 ns" { clk_in {} clk_in~combout {} clk_in~clkctrl {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 93 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 350 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "6.368 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~106 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~110 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~112 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~3 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~127 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9]~feeder sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "6.368 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~106 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~110 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|Equal1~112 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|segment_shift_var~3 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|offset_count~127 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9]~feeder {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] {} } { 0.000ns 1.135ns 0.373ns 0.365ns 0.416ns 1.460ns 0.675ns 0.000ns } { 0.000ns 0.646ns 0.370ns 0.206ns 0.206ns 0.202ns 0.206ns 0.108ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.859 ns" { clk_in clk_in~clkctrl sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "2.859 ns" { clk_in {} clk_in~combout {} clk_in~clkctrl {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[9] {} } { 0.000ns 0.000ns 0.139ns 0.914ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "2.851 ns" { clk_in clk_in~clkctrl sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "2.851 ns" { clk_in {} clk_in~combout {} clk_in~clkctrl {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|counter[6] {} } { 0.000ns 0.000ns 0.139ns 0.906ns } { 0.000ns 1.140ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|irf_reg\[1\]\[3\] register sld_hub:sld_hub_inst\|tdo 101.65 MHz 9.838 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 101.65 MHz between source register \"sld_hub:sld_hub_inst\|irf_reg\[1\]\[3\]\" and destination register \"sld_hub:sld_hub_inst\|tdo\" (period= 9.838 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.646 ns + Longest register register " "Info: + Longest register to register delay is 4.646 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|irf_reg\[1\]\[3\] 1 REG LCFF_X19_Y13_N29 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y13_N29; Fanout = 6; REG Node = 'sld_hub:sld_hub_inst\|irf_reg\[1\]\[3\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|irf_reg[1][3] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 823 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.770 ns) + CELL(0.534 ns) 1.304 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|tdo~424 2 COMB LCCOMB_X19_Y13_N16 1 " "Info: 2: + IC(0.770 ns) + CELL(0.534 ns) = 1.304 ns; Loc. = LCCOMB_X19_Y13_N16; Fanout = 1; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|tdo~424'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.304 ns" { sld_hub:sld_hub_inst|irf_reg[1][3] sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~424 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_signaltap.vhd" 583 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.044 ns) + CELL(0.370 ns) 2.718 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|tdo~425 3 COMB LCCOMB_X18_Y12_N14 1 " "Info: 3: + IC(1.044 ns) + CELL(0.370 ns) = 2.718 ns; Loc. = LCCOMB_X18_Y12_N14; Fanout = 1; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|tdo~425'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.414 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~424 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~425 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_signaltap.vhd" 583 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.319 ns) 3.408 ns sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|tdo~428 4 COMB LCCOMB_X18_Y12_N28 1 " "Info: 4: + IC(0.371 ns) + CELL(0.319 ns) = 3.408 ns; Loc. = LCCOMB_X18_Y12_N28; Fanout = 1; COMB Node = 'sld_signaltap:dds\|sld_signaltap_impl:sld_signaltap_body\|tdo~428'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.690 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~428 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_signaltap.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_signaltap.vhd" 583 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.206 ns) 3.973 ns sld_hub:sld_hub_inst\|tdo~425 5 COMB LCCOMB_X18_Y12_N22 1 " "Info: 5: + IC(0.359 ns) + CELL(0.206 ns) = 3.973 ns; Loc. = LCCOMB_X18_Y12_N22; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|tdo~425'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|tdo~425 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.359 ns) + CELL(0.206 ns) 4.538 ns sld_hub:sld_hub_inst\|tdo~426 6 COMB LCCOMB_X18_Y12_N16 1 " "Info: 6: + IC(0.359 ns) + CELL(0.206 ns) = 4.538 ns; Loc. = LCCOMB_X18_Y12_N16; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|tdo~426'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { sld_hub:sld_hub_inst|tdo~425 sld_hub:sld_hub_inst|tdo~426 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.108 ns) 4.646 ns sld_hub:sld_hub_inst\|tdo 7 REG LCFF_X18_Y12_N17 2 " "Info: 7: + IC(0.000 ns) + CELL(0.108 ns) = 4.646 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|tdo'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.108 ns" { sld_hub:sld_hub_inst|tdo~426 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.743 ns ( 37.52 % ) " "Info: Total cell delay = 1.743 ns ( 37.52 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.903 ns ( 62.48 % ) " "Info: Total interconnect delay = 2.903 ns ( 62.48 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.646 ns" { sld_hub:sld_hub_inst|irf_reg[1][3] sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~424 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|tdo~425 sld_hub:sld_hub_inst|tdo~426 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "4.646 ns" { sld_hub:sld_hub_inst|irf_reg[1][3] {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~424 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|tdo~425 {} sld_hub:sld_hub_inst|tdo~426 {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 0.770ns 1.044ns 0.371ns 0.359ns 0.359ns 0.000ns } { 0.000ns 0.534ns 0.370ns 0.319ns 0.206ns 0.206ns 0.108ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.009 ns - Smallest " "Info: - Smallest clock skew is -0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.374 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.825 ns) + CELL(0.000 ns) 3.825 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 285 " "Info: 2: + IC(3.825 ns) + CELL(0.000 ns) = 3.825 ns; Loc. = CLKCTRL_G3; Fanout = 285; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.825 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.883 ns) + CELL(0.666 ns) 5.374 ns sld_hub:sld_hub_inst\|tdo 3 REG LCFF_X18_Y12_N17 2 " "Info: 3: + IC(0.883 ns) + CELL(0.666 ns) = 5.374 ns; Loc. = LCFF_X18_Y12_N17; Fanout = 2; REG Node = 'sld_hub:sld_hub_inst\|tdo'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.549 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.39 % ) " "Info: Total cell delay = 0.666 ns ( 12.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.708 ns ( 87.61 % ) " "Info: Total interconnect delay = 4.708 ns ( 87.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.374 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.374 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 3.825ns 0.883ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.383 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.383 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y10_N0 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y10_N0; Fanout = 1; CLK Node = 'altera_internal_jtag~TCKUTAP'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.825 ns) + CELL(0.000 ns) 3.825 ns altera_internal_jtag~TCKUTAPclkctrl 2 COMB CLKCTRL_G3 285 " "Info: 2: + IC(3.825 ns) + CELL(0.000 ns) = 3.825 ns; Loc. = CLKCTRL_G3; Fanout = 285; COMB Node = 'altera_internal_jtag~TCKUTAPclkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.825 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.892 ns) + CELL(0.666 ns) 5.383 ns sld_hub:sld_hub_inst\|irf_reg\[1\]\[3\] 3 REG LCFF_X19_Y13_N29 6 " "Info: 3: + IC(0.892 ns) + CELL(0.666 ns) = 5.383 ns; Loc. = LCFF_X19_Y13_N29; Fanout = 6; REG Node = 'sld_hub:sld_hub_inst\|irf_reg\[1\]\[3\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.558 ns" { altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|irf_reg[1][3] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 823 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 12.37 % ) " "Info: Total cell delay = 0.666 ns ( 12.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.717 ns ( 87.63 % ) " "Info: Total interconnect delay = 4.717 ns ( 87.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.383 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|irf_reg[1][3] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.383 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|irf_reg[1][3] {} } { 0.000ns 3.825ns 0.892ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.374 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.374 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 3.825ns 0.883ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.383 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|irf_reg[1][3] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.383 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|irf_reg[1][3] {} } { 0.000ns 3.825ns 0.892ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns + " "Info: + Micro clock to output delay of source is 0.304 ns" {  } { { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 823 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns + " "Info: + Micro setup delay of destination is -0.040 ns" {  } { { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 823 0 0 } } { "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" "" { Text "e:/program files/altera/81/quartus/libraries/megafunctions/sld_hub.vhd" 321 0 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.646 ns" { sld_hub:sld_hub_inst|irf_reg[1][3] sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~424 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~425 sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~428 sld_hub:sld_hub_inst|tdo~425 sld_hub:sld_hub_inst|tdo~426 sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "4.646 ns" { sld_hub:sld_hub_inst|irf_reg[1][3] {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~424 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~425 {} sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|tdo~428 {} sld_hub:sld_hub_inst|tdo~425 {} sld_hub:sld_hub_inst|tdo~426 {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 0.770ns 1.044ns 0.371ns 0.359ns 0.359ns 0.000ns } { 0.000ns 0.534ns 0.370ns 0.319ns 0.206ns 0.206ns 0.108ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.374 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|tdo } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.374 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|tdo {} } { 0.000ns 3.825ns 0.883ns } { 0.000ns 0.000ns 0.666ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.383 ns" { altera_internal_jtag~TCKUTAP altera_internal_jtag~TCKUTAPclkctrl sld_hub:sld_hub_inst|irf_reg[1][3] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.383 ns" { altera_internal_jtag~TCKUTAP {} altera_internal_jtag~TCKUTAPclkctrl {} sld_hub:sld_hub_inst|irf_reg[1][3] {} } { 0.000ns 3.825ns 0.892ns } { 0.000ns 0.000ns 0.666ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}