prev_cmp_dac.tan.qmsg

DDS知识解析

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk_in memory memory ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0 ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\] 180.05 MHz Internal " "Info: Clock \"clk_in\" Internal fmax is restricted to 180.05 MHz between source memory \"ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0\" and destination memory \"ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "2.777 ns 2.777 ns 5.554 ns " "Info: fmax restricted to Clock High delay (2.777 ns) plus Clock Low delay (2.777 ns) : restricted to 5.554 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.641 ns + Longest memory memory " "Info: + Longest memory to memory delay is 3.641 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0 1 MEM M4K_X11_Y18 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X11_Y18; Fanout = 4; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 194 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.641 ns) 3.641 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\] 2 MEM M4K_X11_Y18 1 " "Info: 2: + IC(0.000 ns) + CELL(3.641 ns) = 3.641 ns; Loc. = M4K_X11_Y18; Fanout = 1; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.641 ns ( 100.00 % ) " "Info: Total cell delay = 3.641 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] {} } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.020 ns - Smallest " "Info: - Smallest clock skew is -0.020 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 5.119 ns + Shortest memory " "Info: + Shortest clock path from clock \"clk_in\" to destination memory is 5.119 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_in 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk_in'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns clk_div:inst\|clk_reg 2 REG LCFF_X1_Y9_N17 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y9_N17; Fanout = 3; REG Node = 'clk_div:inst\|clk_reg'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk_in clk_div:inst|clk_reg } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.000 ns) 3.449 ns clk_div:inst\|clk_reg~clkctrl 3 COMB CLKCTRL_G1 60 " "Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 3.449 ns; Loc. = CLKCTRL_G1; Fanout = 60; COMB Node = 'clk_div:inst\|clk_reg~clkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.815 ns) 5.119 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\] 4 MEM M4K_X11_Y18 1 " "Info: 4: + IC(0.855 ns) + CELL(0.815 ns) = 5.119 ns; Loc. = M4K_X11_Y18; Fanout = 1; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[8\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.670 ns" { clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.925 ns ( 57.14 % ) " "Info: Total cell delay = 2.925 ns ( 57.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.194 ns ( 42.86 % ) " "Info: Total interconnect delay = 2.194 ns ( 42.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.119 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.119 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 5.139 ns - Longest memory " "Info: - Longest clock path from clock \"clk_in\" to source memory is 5.139 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_in 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk_in'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns clk_div:inst\|clk_reg 2 REG LCFF_X1_Y9_N17 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y9_N17; Fanout = 3; REG Node = 'clk_div:inst\|clk_reg'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk_in clk_div:inst|clk_reg } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.000 ns) 3.449 ns clk_div:inst\|clk_reg~clkctrl 3 COMB CLKCTRL_G1 60 " "Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 3.449 ns; Loc. = CLKCTRL_G1; Fanout = 60; COMB Node = 'clk_div:inst\|clk_reg~clkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.835 ns) 5.139 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0 4 MEM M4K_X11_Y18 4 " "Info: 4: + IC(0.855 ns) + CELL(0.835 ns) = 5.139 ns; Loc. = M4K_X11_Y18; Fanout = 4; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|ram_block1a8~porta_address_reg0'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.690 ns" { clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 194 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.945 ns ( 57.31 % ) " "Info: Total cell delay = 2.945 ns ( 57.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.194 ns ( 42.69 % ) " "Info: Total interconnect delay = 2.194 ns ( 42.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.139 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.139 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.835ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.119 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.119 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.815ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.139 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.139 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.835ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 194 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.046 ns + " "Info: + Micro setup delay of destination is 0.046 ns" {  } { { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "3.641 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "3.641 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] {} } { 0.000ns 0.000ns } { 0.000ns 3.641ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.119 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.119 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.815ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.139 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.139 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|ram_block1a8~porta_address_reg0 {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.855ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.835ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8] {} } { 0.000ns } { 0.109ns } "" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in da_data\[0\] ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\] 10.361 ns memory " "Info: tco from clock \"clk_in\" to destination pin \"da_data\[0\]\" through memory \"ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\]\" is 10.361 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 5.117 ns + Longest memory " "Info: + Longest clock path from clock \"clk_in\" to source memory is 5.117 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.140 ns) 1.140 ns clk_in 1 CLK PIN_23 2 " "Info: 1: + IC(0.000 ns) + CELL(1.140 ns) = 1.140 ns; Loc. = PIN_23; Fanout = 2; CLK Node = 'clk_in'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 152 -88 80 168 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.522 ns) + CELL(0.970 ns) 2.632 ns clk_div:inst\|clk_reg 2 REG LCFF_X1_Y9_N17 3 " "Info: 2: + IC(0.522 ns) + CELL(0.970 ns) = 2.632 ns; Loc. = LCFF_X1_Y9_N17; Fanout = 3; REG Node = 'clk_div:inst\|clk_reg'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.492 ns" { clk_in clk_div:inst|clk_reg } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.817 ns) + CELL(0.000 ns) 3.449 ns clk_div:inst\|clk_reg~clkctrl 3 COMB CLKCTRL_G1 60 " "Info: 3: + IC(0.817 ns) + CELL(0.000 ns) = 3.449 ns; Loc. = CLKCTRL_G1; Fanout = 60; COMB Node = 'clk_div:inst\|clk_reg~clkctrl'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "0.817 ns" { clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl } "NODE_NAME" } } { "clk_div.v" "" { Text "C:/Users/admin/Desktop/DDS/DAC/clk_div.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.853 ns) + CELL(0.815 ns) 5.117 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\] 4 MEM M4K_X11_Y16 1 " "Info: 4: + IC(0.853 ns) + CELL(0.815 ns) = 5.117 ns; Loc. = M4K_X11_Y16; Fanout = 1; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "1.668 ns" { clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.925 ns ( 57.16 % ) " "Info: Total cell delay = 2.925 ns ( 57.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.192 ns ( 42.84 % ) " "Info: Total interconnect delay = 2.192 ns ( 42.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.117 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.117 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.853ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.815ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.260 ns + " "Info: + Micro clock to output delay of source is 0.260 ns" {  } { { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.984 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.984 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.109 ns) 0.109 ns ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\] 1 MEM M4K_X11_Y16 1 " "Info: 1: + IC(0.000 ns) + CELL(0.109 ns) = 0.109 ns; Loc. = M4K_X11_Y16; Fanout = 1; MEM Node = 'ROM:inst2\|altsyncram:altsyncram_component\|altsyncram_ta31:auto_generated\|q_a\[0\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_ta31.tdf" "" { Text "C:/Users/admin/Desktop/DDS/DAC/db/altsyncram_ta31.tdf" 31 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.609 ns) + CELL(3.266 ns) 4.984 ns da_data\[0\] 2 PIN PIN_187 0 " "Info: 2: + IC(1.609 ns) + CELL(3.266 ns) = 4.984 ns; Loc. = PIN_187; Fanout = 0; PIN Node = 'da_data\[0\]'" {  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.875 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] da_data[0] } "NODE_NAME" } } { "DAC.bdf" "" { Schematic "C:/Users/admin/Desktop/DDS/DAC/DAC.bdf" { { 72 816 992 88 "da_data\[11..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 67.72 % ) " "Info: Total cell delay = 3.375 ns ( 67.72 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.609 ns ( 32.28 % ) " "Info: Total interconnect delay = 1.609 ns ( 32.28 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.984 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] da_data[0] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "4.984 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] {} da_data[0] {} } { 0.000ns 1.609ns } { 0.109ns 3.266ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "5.117 ns" { clk_in clk_div:inst|clk_reg clk_div:inst|clk_reg~clkctrl ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "5.117 ns" { clk_in {} clk_in~combout {} clk_div:inst|clk_reg {} clk_div:inst|clk_reg~clkctrl {} ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.522ns 0.817ns 0.853ns } { 0.000ns 1.140ns 0.970ns 0.000ns 0.815ns } "" } } { "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/program files/altera/81/quartus/bin/TimingClosureFloorplan.fld" "" "4.984 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] da_data[0] } "NODE_NAME" } } { "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/program files/altera/81/quartus/bin/Technology_Viewer.qrui" "4.984 ns" { ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0] {} da_data[0] {} } { 0.000ns 1.609ns } { 0.109ns 3.266ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "154 " "Info: Peak virtual memory: 154 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Aug 08 18:14:24 2009 " "Info: Processing ended: Sat Aug 08 18:14:24 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}