stp1.stp

DDS知识解析

<session jtag_chain="USB-Blaster [USB-0]" jtag_device="@1: EP2C8 (0x020B20DD)" sof_file="" top_level_entity="DAC">
  <display_tree gui_logging_enabled="0">
    <display_branch instance="dds" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
  </display_tree>
  <global_info>
    <single attribute="active instance" value="0"/>
    <single attribute="lock mode" value="36110"/>
    <multi attribute="window position" size="9" value="1280,710,398,124,0,50,124,0,1"/>
  </global_info>
  <instance entity_name="sld_signaltap" is_auto_node="yes" name="dds" source_file="sld_signaltap.vhd">
    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
    <position_info>
      <single attribute="active tab" value="0"/>
      <single attribute="data vertical scroll position" value="0"/>
      <single attribute="data horizontal scroll position" value="0"/>
      <single attribute="zoom level numerator" value="1"/>
      <single attribute="zoom level denominator" value="1"/>
      <single attribute="zoom offset numerator" value="130048"/>
      <single attribute="zoom offset denominator" value="1"/>
    </position_info>
    <signal_set global_temp="1" name="signal_set: 2009/08/08 18:17:30  #0">
      <clock name="clk_in" polarity="posedge" tap_mode="probeonly"/>
      <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="1024" trigger_in_enable="no" trigger_out_enable="no"/>
      <top_entity/>
      <signal_vec>
        <trigger_input_vec>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]" tap_mode="probeonly" type="register"/>
        </trigger_input_vec>
        <data_input_vec>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]" tap_mode="probeonly" type="register"/>
        </data_input_vec>
        <storage_qualifier_input_vec>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]" tap_mode="probeonly" type="register"/>
          <wire name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]" tap_mode="probeonly" type="register"/>
        </storage_qualifier_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a" order="lsb_to_msb" radix="line" state="expand" type="register">
            <net is_signal_inverted="no" name="ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]"/>