dac.qsf

DDS知识解析

# Copyright (C) 1991-2008 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		DAC_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C8Q208C8
set_global_assignment -name TOP_LEVEL_ENTITY DAC
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:36:18  AUGUST 02, 2009"
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name VERILOG_FILE clk_div.v
set_global_assignment -name QIP_FILE ADDR_COUNTER.qip
set_global_assignment -name QIP_FILE ROM.qip
set_global_assignment -name BDF_FILE DAC.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE DAC.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_23 -to clk_in
set_location_assignment PIN_144 -to da_data[10]
set_location_assignment PIN_142 -to da_data[9]
set_location_assignment PIN_139 -to da_data[8]
set_location_assignment PIN_137 -to da_data[7]
set_location_assignment PIN_134 -to da_data[6]
set_location_assignment PIN_128 -to da_data[5]
set_location_assignment PIN_118 -to da_data[4]
set_location_assignment PIN_117 -to da_data[3]
set_location_assignment PIN_116 -to da_data[2]
set_location_assignment PIN_114 -to da_data[1]
set_location_assignment PIN_113 -to da_data[0]
set_global_assignment -name MISC_FILE "G:/FPGA/DAC0802/DAC/DAC.dpf"
set_global_assignment -name HEX_FILE zero4096.hex
set_global_assignment -name HEX_FILE max4096.hex
set_global_assignment -name HEX_FILE mean4096.hex
set_global_assignment -name QIP_FILE COUNTER.qip
set_global_assignment -name HEX_FILE sin1024.hex
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
set_global_assignment -name MISC_FILE "C:/Users/admin/Desktop/DDS/DAC/DAC.dpf"
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name SIGNALTAP_FILE stp1.stp
set_global_assignment -name ENABLE_SIGNALTAP ON
set_global_assignment -name USE_SIGNALTAP_FILE stp2.stp
set_global_assignment -name SIGNALTAP_FILE stp2.stp
set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id ff
set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id ff
set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to clk_in -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[0]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[10]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[11]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[1]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[2]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[3]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[4]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[5]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[6]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[7]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[8]" -section_id ff
set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated|q_a[9]" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=12" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=12" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=60" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=1024" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=39194" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=61347" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=1024" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id ff
set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id ff