dac.map.rpt

DDS知识解析

Analysis & Synthesis report for DAC
Sat Aug 08 18:18:06 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Source assignments for ROM:inst2|altsyncram:altsyncram_component|altsyncram_ta31:auto_generated
  6. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body
  7. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst
  8. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_47p3:auto_generated
  9. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_47p3:auto_generated|altsyncram_ggq1:altsyncram1
 10. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:\adv_point_3_and_more:advance_pointer_counter
 11. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:read_pointer_counter
 12. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_advance_pointer_counter
 13. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|LPM_COUNTER:status_read_pointer_counter
 14. Source assignments for sld_signaltap:dds|sld_signaltap_impl:sld_signaltap_body|sld_rom_sr:crc_rom_sr
 15. Source assignments for sld_hub:sld_hub_inst
 16. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:hub_info_reg
 17. Parameter Settings for User Entity Instance: ROM:inst2|altsyncram:altsyncram_component
 18. Parameter Settings for User Entity Instance: COUNTER:inst4|lpm_add_sub:lpm_add_sub_component
 19. Parameter Settings for Inferred Entity Instance: sld_signaltap:dds
 20. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 21. Partition Status Summary
 22. Partition "sld_hub:sld_hub_inst" Resource Utilization by Entity
 23. Multiplexer Restructuring Statistics (Restructuring Performed)
 24. Partition "sld_signaltap:dds" Resource Utilization by Entity
 25. Registers Removed During Synthesis
 26. Multiplexer Restructuring Statistics (Restructuring Performed)
 27. SignalTap II Logic Analyzer Settings
 28. Analysis & Synthesis Messages
 29. Analysis & Synthesis Suppressed Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sat Aug 08 18:18:06 2009    ;
; Quartus II Version                 ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name                      ; DAC                                      ;
; Top-level Entity Name              ; DAC                                      ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; N/A until Partition Merge                ;
;     Total combinational functions  ; N/A until Partition Merge                ;
;     Dedicated logic registers      ; N/A until Partition Merge                ;
; Total registers                    ; N/A until Partition Merge                ;
; Total pins                         ; N/A until Partition Merge                ;
; Total virtual pins                 ; N/A until Partition Merge                ;
; Total memory bits                  ; N/A until Partition Merge                ;
; Embedded Multiplier 9-bit elements ; N/A until Partition Merge                ;
; Total PLLs                         ; N/A until Partition Merge                ;
+------------------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                            ;
+----------------------------------------------------------------+--------------------+--------------------+
; Option                                                         ; Setting            ; Default Value      ;
+----------------------------------------------------------------+--------------------+--------------------+
; Device                                                         ; EP2C8Q208C8        ;                    ;
; Top-level entity name                                          ; DAC                ; DAC                ;
; Family name                                                    ; Cyclone II         ; Stratix II         ;
; Use Generated Physical Constraints File                        ; Off                ;                    ;
; Use smart compilation                                          ; Off                ; Off                ;
; Restructure Multiplexers                                       ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                            ; Off                ; Off                ;
; Preserve fewer node names                                      ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                      ; Off                ; Off                ;
; Verilog Version                                                ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                   ; VHDL93             ; VHDL93             ;
; State Machine Processing                                       ; Auto               ; Auto               ;
; Safe State Machine                                             ; Off                ; Off                ;
; Extract Verilog State Machines                                 ; On                 ; On                 ;
; Extract VHDL State Machines                                    ; On                 ; On                 ;
; Ignore Verilog initial constructs                              ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                     ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                 ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                        ; On                 ; On                 ;
; Parallel Synthesis                                             ; Off                ; Off                ;
; DSP Block Balancing                                            ; Auto               ; Auto               ;
; NOT Gate Push-Back                                             ; On                 ; On                 ;
; Power-Up Don't Care                                            ; On                 ; On                 ;
; Remove Redundant Logic Cells                                   ; Off                ; Off                ;
; Remove Duplicate Registers                                     ; On                 ; On                 ;
; Ignore CARRY Buffers                                           ; Off                ; Off                ;
; Ignore CASCADE Buffers                                         ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                          ; Off                ; Off                ;