100vhdl+

100vhdl例子

library ieee;
use ieee.std_logic_1164.all;

use work.p_alarm.all;
 
entity tb_alarm_counter is
end tb_alarm_counter;

architecture test of tb_alarm_counter is
component alarm_counter       
       port(new_current_time:in t_clock_time;
            load_new_c    :in std_logic;
            clk           :in std_logic;
            reset         :in std_logic;
            current_time  :out t_clock_time);
end component;

signal new_current_time:t_clock_time;
signal load_new_c:std_logic;
signal clk:std_logic;
signal reset:std_logic;
signal current_time:t_clock_time;

for all:alarm_counter use entity work.alarm_counter(rtl);

begin
u1:alarm_counter
   port map(new_current_time,load_new_c,clk,reset,current_time);

stim:process
  begin
  --initialize
  reset <= '1';
  load_new_c <= '1';
  new_current_time <= (1,2,3,4);

  wait until clk = '1';
  --test vector1
  reset <= '0';
  load_new_c <= '0';
  new_current_time <= (1,2,3,4);

  wait until clk = '1';
  --test vector2
  reset <= '0';
  load_new_c <= '1';
  new_current_time <= (0,8,0,0);

  wait for 100 ns;
  --test vector3
  reset <= '0';
  load_new_c <= '1';
  new_current_time <= (1,9,5,9);

  wait for 200 ns;
  load_new_c <= '0';

  wait for 200 ns;
  --test vector4
  reset <= '0';
  load_new_c <= '1';
  new_current_time <= (2,3,5,9);

  wait for 100 ns;
  load_new_c <= '0';
  wait for 200 ns;

  assert false report "End of simulation!"
  severity error;
  end process;

clk_gen:process
  begin
  clk <= '0';
  while true loop
      wait for 50 ns;
      clk <= not clk;
  end loop;
  end process;
end test;