stp1.stp

采用DDS技术的波形发生器(FPGA实现)

            <net is_signal_inverted="no" name="fcw[2]"/>
            <net is_signal_inverted="no" name="fcw[1]"/>
            <net is_signal_inverted="no" name="fcw[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="output" order="msb_to_lsb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="output[7]"/>
            <net is_signal_inverted="no" name="output[6]"/>
            <net is_signal_inverted="no" name="output[5]"/>
            <net is_signal_inverted="no" name="output[4]"/>
            <net is_signal_inverted="no" name="output[3]"/>
            <net is_signal_inverted="no" name="output[2]"/>
            <net is_signal_inverted="no" name="output[1]"/>
            <net is_signal_inverted="no" name="output[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="mcu_add" order="msb_to_lsb" radix="hex" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="mcu_add[1]"/>
            <net is_signal_inverted="no" name="mcu_add[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="selectwave:inst11|sel" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="selectwave:inst11|sel[1]"/>
            <net is_signal_inverted="no" name="selectwave:inst11|sel[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sin_add:inst2|add_out" order="msb_to_lsb" radix="unsigned_dec" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[7]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[6]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[5]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[4]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[3]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[2]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[1]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sinrom:inst3|address" order="msb_to_lsb" radix="unsigned_dec" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="sinrom:inst3|address[7]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[6]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[5]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[4]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[3]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[2]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[1]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[0]"/>
          </bus>
        </setup_view>
        <data_view>
          <net is_signal_inverted="no" name="a-b"/>
          <net is_signal_inverted="no" name="clear"/>
          <net is_signal_inverted="no" name="cs"/>
          <net is_signal_inverted="no" name="en"/>
          <bus is_signal_inverted="no" link="all" name="fcw" order="msb_to_lsb" radix="unsigned_dec" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="fcw[7]"/>
            <net is_signal_inverted="no" name="fcw[6]"/>
            <net is_signal_inverted="no" name="fcw[5]"/>
            <net is_signal_inverted="no" name="fcw[4]"/>
            <net is_signal_inverted="no" name="fcw[3]"/>
            <net is_signal_inverted="no" name="fcw[2]"/>
            <net is_signal_inverted="no" name="fcw[1]"/>
            <net is_signal_inverted="no" name="fcw[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="output" order="msb_to_lsb" radix="line_signed" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="output[7]"/>
            <net is_signal_inverted="no" name="output[6]"/>
            <net is_signal_inverted="no" name="output[5]"/>
            <net is_signal_inverted="no" name="output[4]"/>
            <net is_signal_inverted="no" name="output[3]"/>
            <net is_signal_inverted="no" name="output[2]"/>
            <net is_signal_inverted="no" name="output[1]"/>
            <net is_signal_inverted="no" name="output[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="mcu_add" order="msb_to_lsb" radix="hex" state="collapse" type="input pin">
            <net is_signal_inverted="no" name="mcu_add[1]"/>
            <net is_signal_inverted="no" name="mcu_add[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="selectwave:inst11|sel" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="selectwave:inst11|sel[1]"/>
            <net is_signal_inverted="no" name="selectwave:inst11|sel[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sin_add:inst2|add_out" order="msb_to_lsb" radix="unsigned_dec" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[7]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[6]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[5]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[4]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[3]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[2]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[1]"/>
            <net is_signal_inverted="no" name="sin_add:inst2|add_out[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="sinrom:inst3|address" order="msb_to_lsb" radix="unsigned_dec" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="sinrom:inst3|address[7]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[6]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[5]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[4]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[3]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[2]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[1]"/>
            <net is_signal_inverted="no" name="sinrom:inst3|address[0]"/>
          </bus>
        </data_view>
      </presentation>
      <trigger CRC="AC8044AF" global_temp="1" name="trigger: 2007/08/06 16:51:50  #1" position="pre" power_up_trigger_mode="false" segment_size="1" trigger_in="dont_care" trigger_out="active high" trigger_type="circular">
        <power_up_trigger position="pre" segment_size="1" trigger_in="dont_care" trigger_out="active high" trigger_type="circular"/>
        <events>
          <level enabled="yes" type="basic">
            <power_up enabled="yes">
            </power_up>
            <op_node/>
          </level>
        </events>
        <data global_temp="1" name="log: 2007/08/06 20:15:32  #0"/>
      </trigger>
    </signal_set>
  </instance>
  <mnemonics/>
  <global_info>
    <single attribute="active instance" value="0"/>
    <multi attribute="window position" size="9" value="802,495,398,98,0,99,0,0,0"/>
  </global_info>
</session>