de2_i2sound.map.rpt

基于I2C 的语音采集与播放 Verilog HDL源代码

;     -- normal mode                          ; 57                             ;
;     -- arithmetic mode                      ; 32                             ;
;                                             ;                                ;
; Total registers                             ; 68                             ;
;     -- Dedicated logic registers            ; 68                             ;
;     -- I/O registers                        ; 0                              ;
;                                             ;                                ;
; I/O pins                                    ; 11                             ;
; Maximum fan-out node                        ; CLOCK_500:inst4|COUNTER_500[9] ;
; Maximum fan-out                             ; 34                             ;
; Total fan-out                               ; 443                            ;
; Average fan-out                             ; 2.64                           ;
+---------------------------------------------+--------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                   ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name          ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+
; |DE2_i2sound               ; 89 (0)            ; 68 (0)       ; 0           ; 0            ; 0       ; 0         ; 11   ; 0            ; |DE2_i2sound                 ;
;    |CLOCK_500:inst4|       ; 40 (40)           ; 36 (36)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_i2sound|CLOCK_500:inst4 ;
;    |i2c:inst|              ; 35 (35)           ; 21 (21)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_i2sound|i2c:inst        ;
;    |keytr:inst1|           ; 14 (14)           ; 11 (11)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |DE2_i2sound|keytr:inst1     ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                              ;
+----------------------------------------+----------------------------------------+
; Register name                          ; Reason for Removal                     ;
+----------------------------------------+----------------------------------------+
; inst4/DATA_A[15]                       ; Stuck at GND due to stuck port data_in ;
; inst4/DATA_A[14]                       ; Stuck at GND due to stuck port data_in ;
; inst4/DATA_A[13]                       ; Stuck at GND due to stuck port data_in ;
; inst4/DATA_A[8]                        ; Stuck at GND due to stuck port data_in ;
; inst/SD[23]                            ; Stuck at GND due to stuck port data_in ;
; inst/SD[22]                            ; Stuck at GND due to stuck port data_in ;
; inst/SD[21]                            ; Stuck at VCC due to stuck port data_in ;
; inst/SD[20]                            ; Stuck at VCC due to stuck port data_in ;
; inst/SD[19]                            ; Stuck at GND due to stuck port data_in ;
; inst/SD[18]                            ; Stuck at VCC due to stuck port data_in ;
; inst/SD[17]                            ; Stuck at GND due to stuck port data_in ;
; inst/SD[16]                            ; Stuck at GND due to stuck port data_in ;
; inst/SD[15]                            ; Stuck at GND due to stuck port data_in ;
; inst/SD[14]                            ; Stuck at GND due to stuck port data_in ;
; inst/SD[13]                            ; Stuck at GND due to stuck port data_in ;
; inst/SD[8]                             ; Stuck at GND due to stuck port data_in ;
; inst4/vol[7]                           ; Lost fanout                            ;
; Total Number of Removed Registers = 17 ;                                        ;
+----------------------------------------+----------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 68    ;
; Number of registers using Synchronous Clear  ; 7     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 16    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 26    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 8:1                ; 5 bits    ; 25 LEs        ; 20 LEs               ; 5 LEs                  ; Yes        ; |DE2_i2sound|CLOCK_500:inst4|DATA_A[6] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.0 Build 33 02/05/2007 SJ Web Edition
    Info: Processing started: Sun Jun 08 13:12:29 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_i2sound -c DE2_i2sound
Info: Found 1 design units, including 1 entities, in source file DE2_i2sound.bdf
    Info: Found entity 1: DE2_i2sound
Info: Found 1 design units, including 1 entities, in source file CLOCK_500.v
    Info: Found entity 1: CLOCK_500
Info: Found 1 design units, including 1 entities, in source file i2c.v
    Info: Found entity 1: i2c
Info: Found 1 design units, including 1 entities, in source file keytr.v
    Info: Found entity 1: keytr
Info: Elaborating entity "DE2_i2sound" for the top level hierarchy
Warning: Pin "AUD_BCLK" not connected
Warning: Pin "AUD_DACLRCK" not connected
Warning: Pin "AUD_ADCLRCK" not connected
Info: Elaborating entity "i2c" for hierarchy "i2c:inst"
Warning (10230): Verilog HDL assignment warning at i2c.v(78): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c.v(77): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at i2c.v(90): truncated value with size 32 to match size of target (6)
Info: Elaborating entity "CLOCK_500" for hierarchy "CLOCK_500:inst4"
Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(72): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(76): truncated value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(82): truncated value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(104): truncated value with size 32 to match size of target (11)
Info: Elaborating entity "keytr" for hierarchy "keytr:inst1"
Warning (10230): Verilog HDL assignment warning at keytr.v(65): truncated value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at keytr.v(71): truncated value with size 32 to match size of target (10)
Warning: Reduced register "CLOCK_500:inst4|DATA_A[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "CLOCK_500:inst4|DATA_A[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "CLOCK_500:inst4|DATA_A[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "CLOCK_500:inst4|DATA_A[8]" with stuck data_in port to stuck value GND
Warning: Reduced register "i2c:inst|SD[23]" with stuck data_in port to stuck value GND
Warning: Reduced register "i2c:inst|SD[22]" with stuck data_in port to stuck value GND
Info: Power-up level of register "i2c:inst|SD[21]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "i2c:inst|SD[21]" with stuck data_in port to stuck value VCC
Info: Power-up level of register "i2c:inst|SD[20]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "i2c:inst|SD[20]" with stuck data_in port to stuck value VCC
Warning: Reduced register "i2c:inst|SD[19]" with stuck data_in port to stuck value GND
Info: Power-up level of register "i2c:inst|SD[18]" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "i2c:inst|SD[18]" with stuck data_in port to stuck value VCC
Warning: Reduced register "i2c:inst|SD[17]" with stuck data_in port to stuck value GND
Warning: Reduced register "i2c:inst|SD[16]" with stuck data_in port to stuck value GND
Warning: Reduced register "i2c:inst|SD[15]" with stuck data_in port to stuck value GND
Warning: Reduced register "i2c:inst|SD[14]" with stuck data_in port to stuck value GND
Warning: Reduced register "i2c:inst|SD[13]" with stuck data_in port to stuck value GND
Warning: Reduced register "i2c:inst|SD[8]" with stuck data_in port to stuck value GND
Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below.
    Info: Register "inst4/vol[7]" lost all its fanouts during netlist optimizations.
Warning: Design contains 3 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "AUD_BCLK"
    Warning: No output dependent on input pin "AUD_DACLRCK"
    Warning: No output dependent on input pin "AUD_ADCLRCK"
Info: Implemented 112 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 4 output pins
    Info: Implemented 1 bidirectional pins
    Info: Implemented 101 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings
    Info: Allocated 125 megabytes of memory during processing
    Info: Processing ended: Sun Jun 08 13:12:30 2008
    Info: Elapsed time: 00:00:01