de2_i2sound.map.qmsg

基于I2C 的语音采集与播放 Verilog HDL源代码

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CLOCK_500:inst4\|DATA_A\[14\] data_in GND " "Warning: Reduced register \"CLOCK_500:inst4\|DATA_A\[14\]\" with stuck data_in port to stuck value GND" {  } { { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CLOCK_500:inst4\|DATA_A\[13\] data_in GND " "Warning: Reduced register \"CLOCK_500:inst4\|DATA_A\[13\]\" with stuck data_in port to stuck value GND" {  } { { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "CLOCK_500:inst4\|DATA_A\[8\] data_in GND " "Warning: Reduced register \"CLOCK_500:inst4\|DATA_A\[8\]\" with stuck data_in port to stuck value GND" {  } { { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[23\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[23\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[22\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[22\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "i2c:inst\|SD\[21\] High " "Info: Power-up level of register \"i2c:inst\|SD\[21\]\" is not specified -- using power-up level of High to minimize register" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[21\] data_in VCC " "Warning: Reduced register \"i2c:inst\|SD\[21\]\" with stuck data_in port to stuck value VCC" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "i2c:inst\|SD\[20\] High " "Info: Power-up level of register \"i2c:inst\|SD\[20\]\" is not specified -- using power-up level of High to minimize register" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[20\] data_in VCC " "Warning: Reduced register \"i2c:inst\|SD\[20\]\" with stuck data_in port to stuck value VCC" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[19\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[19\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "i2c:inst\|SD\[18\] High " "Info: Power-up level of register \"i2c:inst\|SD\[18\]\" is not specified -- using power-up level of High to minimize register" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[18\] data_in VCC " "Warning: Reduced register \"i2c:inst\|SD\[18\]\" with stuck data_in port to stuck value VCC" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[17\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[17\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[16\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[16\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[15\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[15\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[14\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[14\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[13\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[13\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "i2c:inst\|SD\[8\] data_in GND " "Warning: Reduced register \"i2c:inst\|SD\[8\]\" with stuck data_in port to stuck value GND" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 98 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "1 1 " "Info: 1 registers lost all their fanouts during netlist optimizations. The first 1 are displayed below." { { "Info" "ISCL_SCL_LOST_FANOUT_MSG_SUB" "inst4/vol\[7\] " "Info: Register \"inst4/vol\[7\]\" lost all its fanouts during netlist optimizations." {  } {  } 0 0 "Register \"%1!s!\" lost all its fanouts during netlist optimizations." 0 0}  } {  } 0 0 "%1!d! registers lost all their fanouts during netlist optimizations. The first %2!d! are displayed below." 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "3 " "Warning: Design contains 3 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "AUD_BCLK " "Warning: No output dependent on input pin \"AUD_BCLK\"" {  } { { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 400 1048 1216 416 "AUD_BCLK" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "AUD_DACLRCK " "Warning: No output dependent on input pin \"AUD_DACLRCK\"" {  } { { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 432 1048 1216 448 "AUD_DACLRCK" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0} { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "AUD_ADCLRCK " "Warning: No output dependent on input pin \"AUD_ADCLRCK\"" {  } { { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 448 1048 1216 464 "AUD_ADCLRCK" "" } } } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "112 " "Info: Implemented 112 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "4 " "Info: Implemented 4 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "1 " "Info: Implemented 1 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "101 " "Info: Implemented 101 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 32 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 32 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Allocated 125 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 08 13:12:30 2008 " "Info: Processing ended: Sun Jun 08 13:12:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}