de2_i2sound.tan.qmsg

基于I2C 的语音采集与播放 Verilog HDL源代码

{ "Info" "ITDB_FULL_TCO_RESULT" "50MHZ I2C_SCLK i2c:inst\|SD_COUNTER\[3\] 13.864 ns register " "Info: tco from clock \"50MHZ\" to destination pin \"I2C_SCLK\" through register \"i2c:inst\|SD_COUNTER\[3\]\" is 13.864 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ source 5.124 ns + Longest register " "Info: + Longest clock path from clock \"50MHZ\" to source register is 5.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns 50MHZ 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = '50MHZ'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns 50MHZ~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = '50MHZ~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { 50MHZ 50MHZ~clkctrl } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns CLOCK_500:inst4\|COUNTER_500\[9\] 3 REG LCFF_X1_Y18_N19 4 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 4; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.810 ns" { 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.000 ns) 3.570 ns CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl 4 COMB CLKCTRL_G3 32 " "Info: 4: + IC(0.643 ns) + CELL(0.000 ns) = 3.570 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.537 ns) 5.124 ns i2c:inst\|SD_COUNTER\[3\] 5 REG LCFF_X36_Y19_N25 14 " "Info: 5: + IC(1.017 ns) + CELL(0.537 ns) = 5.124 ns; Loc. = LCFF_X36_Y19_N25; Fanout = 14; REG Node = 'i2c:inst\|SD_COUNTER\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[3] } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.34 % ) " "Info: Total cell delay = 2.323 ns ( 45.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.801 ns ( 54.66 % ) " "Info: Total interconnect delay = 2.801 ns ( 54.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.124 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.124 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.490 ns + Longest register pin " "Info: + Longest register to pin delay is 8.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns i2c:inst\|SD_COUNTER\[3\] 1 REG LCFF_X36_Y19_N25 14 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y19_N25; Fanout = 14; REG Node = 'i2c:inst\|SD_COUNTER\[3\]'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { i2c:inst|SD_COUNTER[3] } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.347 ns) + CELL(0.410 ns) 0.757 ns i2c:inst\|LessThan2~72 2 COMB LCCOMB_X36_Y19_N4 2 " "Info: 2: + IC(0.347 ns) + CELL(0.410 ns) = 0.757 ns; Loc. = LCCOMB_X36_Y19_N4; Fanout = 2; COMB Node = 'i2c:inst\|LessThan2~72'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.757 ns" { i2c:inst|SD_COUNTER[3] i2c:inst|LessThan2~72 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 90 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.718 ns) + CELL(0.150 ns) 1.625 ns i2c:inst\|I2C_SCLK~252 3 COMB LCCOMB_X36_Y20_N12 1 " "Info: 3: + IC(0.718 ns) + CELL(0.150 ns) = 1.625 ns; Loc. = LCCOMB_X36_Y20_N12; Fanout = 1; COMB Node = 'i2c:inst\|I2C_SCLK~252'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.868 ns" { i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.245 ns) + CELL(0.150 ns) 2.020 ns i2c:inst\|I2C_SCLK~253 4 COMB LCCOMB_X36_Y20_N16 1 " "Info: 4: + IC(0.245 ns) + CELL(0.150 ns) = 2.020 ns; Loc. = LCCOMB_X36_Y20_N16; Fanout = 1; COMB Node = 'i2c:inst\|I2C_SCLK~253'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.395 ns" { i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 62 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.662 ns) + CELL(2.808 ns) 8.490 ns I2C_SCLK 5 PIN PIN_A6 0 " "Info: 5: + IC(3.662 ns) + CELL(2.808 ns) = 8.490 ns; Loc. = PIN_A6; Fanout = 0; PIN Node = 'I2C_SCLK'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "6.470 ns" { i2c:inst|I2C_SCLK~253 I2C_SCLK } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 112 1024 1200 128 "I2C_SCLK" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.518 ns ( 41.44 % ) " "Info: Total cell delay = 3.518 ns ( 41.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.972 ns ( 58.56 % ) " "Info: Total interconnect delay = 4.972 ns ( 58.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.490 ns" { i2c:inst|SD_COUNTER[3] i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 I2C_SCLK } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.490 ns" { i2c:inst|SD_COUNTER[3] i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 I2C_SCLK } { 0.000ns 0.347ns 0.718ns 0.245ns 3.662ns } { 0.000ns 0.410ns 0.150ns 0.150ns 2.808ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.124 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.124 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.490 ns" { i2c:inst|SD_COUNTER[3] i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 I2C_SCLK } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.490 ns" { i2c:inst|SD_COUNTER[3] i2c:inst|LessThan2~72 i2c:inst|I2C_SCLK~252 i2c:inst|I2C_SCLK~253 I2C_SCLK } { 0.000ns 0.347ns 0.718ns 0.245ns 3.662ns } { 0.000ns 0.410ns 0.150ns 0.150ns 2.808ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "AUD_ADCDAT AUD_DACDAT 8.933 ns Longest " "Info: Longest tpd from source pin \"AUD_ADCDAT\" to destination pin \"AUD_DACDAT\" is 8.933 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.870 ns) 0.870 ns AUD_ADCDAT 1 PIN PIN_B5 1 " "Info: 1: + IC(0.000 ns) + CELL(0.870 ns) = 0.870 ns; Loc. = PIN_B5; Fanout = 1; PIN Node = 'AUD_ADCDAT'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { AUD_ADCDAT } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 368 1048 1216 384 "AUD_ADCDAT" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.245 ns) + CELL(2.818 ns) 8.933 ns AUD_DACDAT 2 PIN PIN_A4 0 " "Info: 2: + IC(5.245 ns) + CELL(2.818 ns) = 8.933 ns; Loc. = PIN_A4; Fanout = 0; PIN Node = 'AUD_DACDAT'" {  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.063 ns" { AUD_ADCDAT AUD_DACDAT } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 280 1032 1208 296 "AUD_DACDAT" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.688 ns ( 41.29 % ) " "Info: Total cell delay = 3.688 ns ( 41.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.245 ns ( 58.71 % ) " "Info: Total interconnect delay = 5.245 ns ( 58.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.933 ns" { AUD_ADCDAT AUD_DACDAT } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.933 ns" { AUD_ADCDAT AUD_ADCDAT~combout AUD_DACDAT } { 0.000ns 0.000ns 5.245ns } { 0.000ns 0.870ns 2.818ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0}
{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." {  } {  } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0}