📄 de2_i2sound.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "keytr:inst1\|KEYON " "Info: Detected ripple clock \"keytr:inst1\|KEYON\" as buffer" { } { { "keytr.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/keytr.v" 57 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "keytr:inst1\|KEYON" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "i2c:inst\|END " "Info: Detected ripple clock \"i2c:inst\|END\" as buffer" { } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "i2c:inst\|END" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "CLOCK_500:inst4\|COUNTER_500\[9\] " "Info: Detected ripple clock \"CLOCK_500:inst4\|COUNTER_500\[9\]\" as buffer" { } { { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } { "d:/altera/70/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/70/quartus/bin/Assignment Editor.qase" 1 { { 0 "CLOCK_500:inst4\|COUNTER_500\[9\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "50MHZ register CLOCK_500:inst4\|address\[1\] register i2c:inst\|SD_COUNTER\[0\] 14.043 ns " "Info: Slack time is 14.043 ns for clock \"50MHZ\" between source register \"CLOCK_500:inst4\|address\[1\]\" and destination register \"i2c:inst\|SD_COUNTER\[0\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "167.87 MHz 5.957 ns " "Info: Fmax is 167.87 MHz (period= 5.957 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "16.363 ns + Largest register register " "Info: + Largest register to register requirement is 16.363 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "20.000 ns + " "Info: + Setup relationship between source and destination is 20.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 20.000 ns " "Info: + Latch edge is 20.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination 50MHZ 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"50MHZ\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source 50MHZ 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"50MHZ\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.423 ns + Largest " "Info: + Largest clock skew is -3.423 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ destination 5.124 ns + Shortest register " "Info: + Shortest clock path from clock \"50MHZ\" to destination register is 5.124 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns 50MHZ 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = '50MHZ'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns 50MHZ~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = '50MHZ~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { 50MHZ 50MHZ~clkctrl } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns CLOCK_500:inst4\|COUNTER_500\[9\] 3 REG LCFF_X1_Y18_N19 4 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 4; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.810 ns" { 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.000 ns) 3.570 ns CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl 4 COMB CLKCTRL_G3 32 " "Info: 4: + IC(0.643 ns) + CELL(0.000 ns) = 3.570 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.017 ns) + CELL(0.537 ns) 5.124 ns i2c:inst\|SD_COUNTER\[0\] 5 REG LCFF_X36_Y19_N19 15 " "Info: 5: + IC(1.017 ns) + CELL(0.537 ns) = 5.124 ns; Loc. = LCFF_X36_Y19_N19; Fanout = 15; REG Node = 'i2c:inst\|SD_COUNTER\[0\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.554 ns" { CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 45.34 % ) " "Info: Total cell delay = 2.323 ns ( 45.34 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.801 ns ( 54.66 % ) " "Info: Total interconnect delay = 2.801 ns ( 54.66 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.124 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.124 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ source 8.547 ns - Longest register " "Info: - Longest clock path from clock \"50MHZ\" to source register is 8.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns 50MHZ 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = '50MHZ'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns 50MHZ~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = '50MHZ~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { 50MHZ 50MHZ~clkctrl } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns CLOCK_500:inst4\|COUNTER_500\[9\] 3 REG LCFF_X1_Y18_N19 4 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 4; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.810 ns" { 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.000 ns) 3.570 ns CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl 4 COMB CLKCTRL_G3 32 " "Info: 4: + IC(0.643 ns) + CELL(0.000 ns) = 3.570 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.787 ns) 5.372 ns i2c:inst\|END 5 REG LCFF_X36_Y20_N19 3 " "Info: 5: + IC(1.015 ns) + CELL(0.787 ns) = 5.372 ns; Loc. = LCFF_X36_Y20_N19; Fanout = 3; REG Node = 'i2c:inst\|END'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.802 ns" { CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.636 ns) + CELL(0.000 ns) 7.008 ns i2c:inst\|END~clkctrl 6 COMB CLKCTRL_G6 18 " "Info: 6: + IC(1.636 ns) + CELL(0.000 ns) = 7.008 ns; Loc. = CLKCTRL_G6; Fanout = 18; COMB Node = 'i2c:inst\|END~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.636 ns" { i2c:inst|END i2c:inst|END~clkctrl } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.002 ns) + CELL(0.537 ns) 8.547 ns CLOCK_500:inst4\|address\[1\] 7 REG LCFF_X36_Y19_N7 15 " "Info: 7: + IC(1.002 ns) + CELL(0.537 ns) = 8.547 ns; Loc. = LCFF_X36_Y19_N7; Fanout = 15; REG Node = 'CLOCK_500:inst4\|address\[1\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.539 ns" { i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 76 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.110 ns ( 36.39 % ) " "Info: Total cell delay = 3.110 ns ( 36.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.437 ns ( 63.61 % ) " "Info: Total interconnect delay = 5.437 ns ( 63.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.547 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.547 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.636ns 1.002ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.124 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.124 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.547 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.547 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.636ns 1.002ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 76 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" { } { { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.124 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.124 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.547 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.547 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.636ns 1.002ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.320 ns - Longest register register " "Info: - Longest register to register delay is 2.320 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLOCK_500:inst4\|address\[1\] 1 REG LCFF_X36_Y19_N7 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X36_Y19_N7; Fanout = 15; REG Node = 'CLOCK_500:inst4\|address\[1\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|address[1] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 76 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.329 ns) + CELL(0.438 ns) 0.767 ns CLOCK_500:inst4\|LessThan0~84 2 COMB LCCOMB_X36_Y19_N2 1 " "Info: 2: + IC(0.329 ns) + CELL(0.438 ns) = 0.767 ns; Loc. = LCCOMB_X36_Y19_N2; Fanout = 1; COMB Node = 'CLOCK_500:inst4\|LessThan0~84'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.767 ns" { CLOCK_500:inst4|address[1] CLOCK_500:inst4|LessThan0~84 } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.250 ns) + CELL(0.150 ns) 1.167 ns CLOCK_500:inst4\|LessThan0~85 3 COMB LCCOMB_X36_Y19_N0 7 " "Info: 3: + IC(0.250 ns) + CELL(0.150 ns) = 1.167 ns; Loc. = LCCOMB_X36_Y19_N0; Fanout = 7; COMB Node = 'CLOCK_500:inst4\|LessThan0~85'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.400 ns" { CLOCK_500:inst4|LessThan0~84 CLOCK_500:inst4|LessThan0~85 } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 72 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.253 ns) + CELL(0.150 ns) 1.570 ns CLOCK_500:inst4\|GO~33 4 COMB LCCOMB_X36_Y19_N16 6 " "Info: 4: + IC(0.253 ns) + CELL(0.150 ns) = 1.570 ns; Loc. = LCCOMB_X36_Y19_N16; Fanout = 6; COMB Node = 'CLOCK_500:inst4\|GO~33'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.403 ns" { CLOCK_500:inst4|LessThan0~85 CLOCK_500:inst4|GO~33 } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 58 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(0.510 ns) 2.320 ns i2c:inst\|SD_COUNTER\[0\] 5 REG LCFF_X36_Y19_N19 15 " "Info: 5: + IC(0.240 ns) + CELL(0.510 ns) = 2.320 ns; Loc. = LCFF_X36_Y19_N19; Fanout = 15; REG Node = 'i2c:inst\|SD_COUNTER\[0\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.750 ns" { CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 91 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.248 ns ( 53.79 % ) " "Info: Total cell delay = 1.248 ns ( 53.79 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.072 ns ( 46.21 % ) " "Info: Total interconnect delay = 1.072 ns ( 46.21 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.320 ns" { CLOCK_500:inst4|address[1] CLOCK_500:inst4|LessThan0~84 CLOCK_500:inst4|LessThan0~85 CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.320 ns" { CLOCK_500:inst4|address[1] CLOCK_500:inst4|LessThan0~84 CLOCK_500:inst4|LessThan0~85 CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[0] } { 0.000ns 0.329ns 0.250ns 0.253ns 0.240ns } { 0.000ns 0.438ns 0.150ns 0.150ns 0.510ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "5.124 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "5.124 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|SD_COUNTER[0] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.017ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.547 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.547 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|address[1] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.636ns 1.002ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "2.320 ns" { CLOCK_500:inst4|address[1] CLOCK_500:inst4|LessThan0~84 CLOCK_500:inst4|LessThan0~85 CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[0] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "2.320 ns" { CLOCK_500:inst4|address[1] CLOCK_500:inst4|LessThan0~84 CLOCK_500:inst4|LessThan0~85 CLOCK_500:inst4|GO~33 i2c:inst|SD_COUNTER[0] } { 0.000ns 0.329ns 0.250ns 0.253ns 0.240ns } { 0.000ns 0.438ns 0.150ns 0.150ns 0.510ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "50MHZ register CLOCK_500:inst4\|vol\[3\] register CLOCK_500:inst4\|DATA_A\[3\] 381 ps " "Info: Minimum slack time is 381 ps for clock \"50MHZ\" between source register \"CLOCK_500:inst4\|vol\[3\]\" and destination register \"CLOCK_500:inst4\|DATA_A\[3\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.030 ns + Shortest register register " "Info: + Shortest register to register delay is 1.030 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CLOCK_500:inst4\|vol\[3\] 1 REG LCFF_X35_Y22_N17 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X35_Y22_N17; Fanout = 3; REG Node = 'CLOCK_500:inst4\|vol\[3\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { CLOCK_500:inst4|vol[3] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.796 ns) + CELL(0.150 ns) 0.946 ns CLOCK_500:inst4\|Mux3~68 2 COMB LCCOMB_X35_Y19_N22 1 " "Info: 2: + IC(0.796 ns) + CELL(0.150 ns) = 0.946 ns; Loc. = LCCOMB_X35_Y19_N22; Fanout = 1; COMB Node = 'CLOCK_500:inst4\|Mux3~68'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { CLOCK_500:inst4|vol[3] CLOCK_500:inst4|Mux3~68 } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 100 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.030 ns CLOCK_500:inst4\|DATA_A\[3\] 3 REG LCFF_X35_Y19_N23 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.030 ns; Loc. = LCFF_X35_Y19_N23; Fanout = 1; REG Node = 'CLOCK_500:inst4\|DATA_A\[3\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { CLOCK_500:inst4|Mux3~68 CLOCK_500:inst4|DATA_A[3] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.234 ns ( 22.72 % ) " "Info: Total cell delay = 0.234 ns ( 22.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.796 ns ( 77.28 % ) " "Info: Total interconnect delay = 0.796 ns ( 77.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.030 ns" { CLOCK_500:inst4|vol[3] CLOCK_500:inst4|Mux3~68 CLOCK_500:inst4|DATA_A[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.030 ns" { CLOCK_500:inst4|vol[3] CLOCK_500:inst4|Mux3~68 CLOCK_500:inst4|DATA_A[3] } { 0.000ns 0.796ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.649 ns - Smallest register register " "Info: - Smallest register to register requirement is 0.649 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination 50MHZ 20.000 ns 0.000 ns 50 " "Info: Clock period of Destination clock \"50MHZ\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source 50MHZ 20.000 ns 0.000 ns 50 " "Info: Clock period of Source clock \"50MHZ\" is 20.000 ns with offset of 0.000 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.633 ns + Smallest " "Info: + Smallest clock skew is 0.633 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ destination 8.546 ns + Longest register " "Info: + Longest clock path from clock \"50MHZ\" to destination register is 8.546 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns 50MHZ 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = '50MHZ'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns 50MHZ~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = '50MHZ~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { 50MHZ 50MHZ~clkctrl } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns CLOCK_500:inst4\|COUNTER_500\[9\] 3 REG LCFF_X1_Y18_N19 4 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 4; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.810 ns" { 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.000 ns) 3.570 ns CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl 4 COMB CLKCTRL_G3 32 " "Info: 4: + IC(0.643 ns) + CELL(0.000 ns) = 3.570 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.787 ns) 5.372 ns i2c:inst\|END 5 REG LCFF_X36_Y20_N19 3 " "Info: 5: + IC(1.015 ns) + CELL(0.787 ns) = 5.372 ns; Loc. = LCFF_X36_Y20_N19; Fanout = 3; REG Node = 'i2c:inst\|END'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.802 ns" { CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.636 ns) + CELL(0.000 ns) 7.008 ns i2c:inst\|END~clkctrl 6 COMB CLKCTRL_G6 18 " "Info: 6: + IC(1.636 ns) + CELL(0.000 ns) = 7.008 ns; Loc. = CLKCTRL_G6; Fanout = 18; COMB Node = 'i2c:inst\|END~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.636 ns" { i2c:inst|END i2c:inst|END~clkctrl } "NODE_NAME" } } { "i2c.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/i2c.v" 63 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.537 ns) 8.546 ns CLOCK_500:inst4\|DATA_A\[3\] 7 REG LCFF_X35_Y19_N23 1 " "Info: 7: + IC(1.001 ns) + CELL(0.537 ns) = 8.546 ns; Loc. = LCFF_X35_Y19_N23; Fanout = 1; REG Node = 'CLOCK_500:inst4\|DATA_A\[3\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.538 ns" { i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.110 ns ( 36.39 % ) " "Info: Total cell delay = 3.110 ns ( 36.39 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.436 ns ( 63.61 % ) " "Info: Total interconnect delay = 5.436 ns ( 63.61 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.546 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.546 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.636ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "50MHZ source 7.913 ns - Shortest register " "Info: - Shortest clock path from clock \"50MHZ\" to source register is 7.913 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns 50MHZ 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = '50MHZ'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "" { 50MHZ } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns 50MHZ~clkctrl 2 COMB CLKCTRL_G2 11 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 11; COMB Node = '50MHZ~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.118 ns" { 50MHZ 50MHZ~clkctrl } "NODE_NAME" } } { "DE2_i2sound.bdf" "" { Schematic "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 96 136 304 112 "50MHZ" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns CLOCK_500:inst4\|COUNTER_500\[9\] 3 REG LCFF_X1_Y18_N19 4 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X1_Y18_N19; Fanout = 4; REG Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.810 ns" { 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.643 ns) + CELL(0.000 ns) 3.570 ns CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl 4 COMB CLKCTRL_G3 32 " "Info: 4: + IC(0.643 ns) + CELL(0.000 ns) = 3.570 ns; Loc. = CLKCTRL_G3; Fanout = 32; COMB Node = 'CLOCK_500:inst4\|COUNTER_500\[9\]~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "0.643 ns" { CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 103 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.787 ns) 5.372 ns keytr:inst1\|KEYON 5 REG LCFF_X33_Y35_N29 2 " "Info: 5: + IC(1.015 ns) + CELL(0.787 ns) = 5.372 ns; Loc. = LCFF_X33_Y35_N29; Fanout = 2; REG Node = 'keytr:inst1\|KEYON'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.802 ns" { CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON } "NODE_NAME" } } { "keytr.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/keytr.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.003 ns) + CELL(0.000 ns) 6.375 ns keytr:inst1\|KEYON~clkctrl 6 COMB CLKCTRL_G11 13 " "Info: 6: + IC(1.003 ns) + CELL(0.000 ns) = 6.375 ns; Loc. = CLKCTRL_G11; Fanout = 13; COMB Node = 'keytr:inst1\|KEYON~clkctrl'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.003 ns" { keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl } "NODE_NAME" } } { "keytr.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/keytr.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.001 ns) + CELL(0.537 ns) 7.913 ns CLOCK_500:inst4\|vol\[3\] 7 REG LCFF_X35_Y22_N17 3 " "Info: 7: + IC(1.001 ns) + CELL(0.537 ns) = 7.913 ns; Loc. = LCFF_X35_Y22_N17; Fanout = 3; REG Node = 'CLOCK_500:inst4\|vol\[3\]'" { } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.538 ns" { keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } "NODE_NAME" } } { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 81 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.110 ns ( 39.30 % ) " "Info: Total cell delay = 3.110 ns ( 39.30 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.803 ns ( 60.70 % ) " "Info: Total interconnect delay = 4.803 ns ( 60.70 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.913 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.913 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.003ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.546 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.546 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.636ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.913 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.913 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.003ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" { } { { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 81 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" { } { { "CLOCK_500.v" "" { Text "E:/FPGA/DE2 System V1.6 (F)/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 85 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.546 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.546 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.636ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.913 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.913 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.003ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "1.030 ns" { CLOCK_500:inst4|vol[3] CLOCK_500:inst4|Mux3~68 CLOCK_500:inst4|DATA_A[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "1.030 ns" { CLOCK_500:inst4|vol[3] CLOCK_500:inst4|Mux3~68 CLOCK_500:inst4|DATA_A[3] } { 0.000ns 0.796ns 0.000ns } { 0.000ns 0.150ns 0.084ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "8.546 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "8.546 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl i2c:inst|END i2c:inst|END~clkctrl CLOCK_500:inst4|DATA_A[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.636ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } { "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/70/quartus/bin/TimingClosureFloorplan.fld" "" "7.913 ns" { 50MHZ 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } "NODE_NAME" } } { "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/70/quartus/bin/Technology_Viewer.qrui" "7.913 ns" { 50MHZ 50MHZ~combout 50MHZ~clkctrl CLOCK_500:inst4|COUNTER_500[9] CLOCK_500:inst4|COUNTER_500[9]~clkctrl keytr:inst1|KEYON keytr:inst1|KEYON~clkctrl CLOCK_500:inst4|vol[3] } { 0.000ns 0.000ns 0.118ns 1.023ns 0.643ns 1.015ns 1.003ns 1.001ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.787ns 0.000ns 0.537ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
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