prev_cmp_de2_i2sound.qmsg

基于I2C 的语音采集与播放 Verilog HDL源代码

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jun 20 16:33:13 2007 " "Info: Processing started: Wed Jun 20 16:33:13 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DE2_i2sound -c DE2_i2sound " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DE2_i2sound -c DE2_i2sound" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DE2_i2sound.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DE2_i2sound.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DE2_i2sound " "Info: Found entity 1: DE2_i2sound" {  } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLOCK_500.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CLOCK_500.v" { { "Info" "ISGN_ENTITY_NAME" "1 CLOCK_500 " "Info: Found entity 1: CLOCK_500" {  } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 44 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "i2c.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file i2c.v" { { "Info" "ISGN_ENTITY_NAME" "1 i2c " "Info: Found entity 1: i2c" {  } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "keytr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file keytr.v" { { "Info" "ISGN_ENTITY_NAME" "1 keytr " "Info: Found entity 1: keytr" {  } { { "keytr.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/keytr.v" 47 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DE2_i2sound " "Info: Elaborating entity \"DE2_i2sound\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Warning" "WGDFX_PIN_IGNORED" "AUD_BCLK " "Warning: Pin \"AUD_BCLK\" not connected" {  } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 400 1048 1216 416 "AUD_BCLK" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0 "" 0}
{ "Warning" "WGDFX_PIN_IGNORED" "AUD_DACLRCK " "Warning: Pin \"AUD_DACLRCK\" not connected" {  } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 432 1048 1216 448 "AUD_DACLRCK" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0 "" 0}
{ "Warning" "WGDFX_PIN_IGNORED" "AUD_ADCLRCK " "Warning: Pin \"AUD_ADCLRCK\" not connected" {  } { { "DE2_i2sound.bdf" "" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 448 1048 1216 464 "AUD_ADCLRCK" "" } } } }  } 0 0 "Pin \"%1!s!\" not connected" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "i2c i2c:inst " "Info: Elaborating entity \"i2c\" for hierarchy \"i2c:inst\"" {  } { { "DE2_i2sound.bdf" "inst" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 72 696 936 232 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(78) " "Warning (10230): Verilog HDL assignment warning at i2c.v(78): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 78 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 i2c.v(77) " "Warning (10230): Verilog HDL assignment warning at i2c.v(77): truncated value with size 32 to match size of target (1)" {  } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 77 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 i2c.v(90) " "Warning (10230): Verilog HDL assignment warning at i2c.v(90): truncated value with size 32 to match size of target (6)" {  } { { "i2c.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/i2c.v" 90 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CLOCK_500 CLOCK_500:inst4 " "Info: Elaborating entity \"CLOCK_500\" for hierarchy \"CLOCK_500:inst4\"" {  } { { "DE2_i2sound.bdf" "inst4" { Schematic "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/DE2_i2sound.bdf" { { 72 400 552 200 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 CLOCK_500.v(72) " "Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(72): truncated value with size 32 to match size of target (1)" {  } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 72 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 CLOCK_500.v(76) " "Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(76): truncated value with size 32 to match size of target (6)" {  } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 76 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 CLOCK_500.v(82) " "Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(82): truncated value with size 32 to match size of target (8)" {  } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 82 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 CLOCK_500.v(104) " "Warning (10230): Verilog HDL assignment warning at CLOCK_500.v(104): truncated value with size 32 to match size of target (11)" {  } { { "CLOCK_500.v" "" { Text "D:/keith_temp/quartusII/DE2_System_v1.5/DE2_System_v1.5/DE2_demonstrations/DE2_i2sound/CLOCK_500.v" 104 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}