📄 mydsp2812.map.eqn
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--A1L67 is GPIOB[9]~59
A1L67_or_out = A1L57;
A1L67 = A1L67_or_out;
--A1L48 is GPIOB~62
A1L48_p1_out = SW[1] & CPLD_FRNB;
A1L48_or_out = A1L48_p1_out;
A1L48 = A1L48_or_out;
--A1L58 is GPIOB~64
A1L58_p1_out = SW[2] & USB_FLAGB;
A1L58_or_out = A1L58_p1_out;
A1L58 = A1L58_or_out;
--A1L68 is GPIOB~66
A1L68_p1_out = SW[3] & USB_FLAGC;
A1L68_or_out = A1L68_p1_out;
A1L68 = A1L68_or_out;
--A1L78 is GPIOB~68
A1L78_p1_out = SW[4] & USB_RDY;
A1L78_or_out = A1L78_p1_out;
A1L78 = A1L78_or_out;
--A1L09 is INT1~9
A1L09_p1_out = SW[4] & USB_INTn;
A1L09_or_out = A1L09_p1_out;
A1L09 = A1L09_or_out;
--A1L74 is DSP_ADDR[5]~50
A1L74_or_out = DSP_ADDR[5];
A1L74 = A1L74_or_out;
--A1L541 is SPI_CLK~2
A1L541_or_out = SPI_CLK;
A1L541 = A1L541_or_out;
--A1L84 is DSP_ADDR[5]~52
A1L84_or_out = DSP_ADDR[5];
A1L84 = A1L84_or_out;
--A1L05 is DSP_ADDR[6]~54
A1L05_or_out = DSP_ADDR[6];
A1L05 = A1L05_or_out;
--A1L54 is DSP_ADDR[4]~56
A1L54_or_out = DSP_ADDR[4];
A1L54 = A1L54_or_out;
--A1L731 is RDn~2
A1L731_or_out = RDn;
A1L731 = A1L731_or_out;
--A1L31 is CPLD_LED3~11
A1L31_p1_out = !GLOBAL(WEn) & !CS0AND1n & DSP_ADDR[7];
A1L31_or_out = A1L31_p1_out;
A1L31 = A1L31_or_out;
--A1L661 is WEn~13
A1L661_or_out = GLOBAL(WEn);
A1L661 = A1L661_or_out;
--A1L941 is SPI_SIMO~6
A1L941_or_out = A1L841;
A1L941 = A1L941_or_out;
--A1L751 is USB_CSn~8
A1L751_p1_out = GLOBAL(WEn) & RDn;
A1L751_or_out = DSP_ADDR[7] # A1L751_p1_out # DSP_ADDR[4] # !DSP_ADDR[3] # CS0AND1n;
A1L751 = A1L751_or_out;
--A1L361 is USB_PKTEND~7
A1L361_p1_out = DSP_ADDR[4] & !GLOBAL(WEn) & DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7];
A1L361_or_out = A1L361_p1_out;
A1L361 = !(A1L361_or_out);
--A1L37 is GPIOB[8]~71
A1L37_or_out = A1L27;
A1L37 = A1L37_or_out;
--LED[8] is LED[8]
LED[8]_or_out = A1L86;
LED[8]_reg_input = LED[8]_or_out;
LED[8]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[8] = DFFE(LED[8]_reg_input, GLOBAL(WEn), , , LED[8]_p3_out);
--LED[7] is LED[7]
LED[7]_or_out = A1L66;
LED[7]_reg_input = LED[7]_or_out;
LED[7]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[7] = DFFE(LED[7]_reg_input, GLOBAL(WEn), , , LED[7]_p3_out);
--LED[6] is LED[6]
LED[6]_or_out = A1L46;
LED[6]_reg_input = LED[6]_or_out;
LED[6]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[6] = DFFE(LED[6]_reg_input, GLOBAL(WEn), , , LED[6]_p3_out);
--LED[5] is LED[5]
LED[5]_or_out = A1L26;
LED[5]_reg_input = LED[5]_or_out;
LED[5]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[5] = DFFE(LED[5]_reg_input, GLOBAL(WEn), , , LED[5]_p3_out);
--LED[4] is LED[4]
LED[4]_or_out = A1L06;
LED[4]_reg_input = LED[4]_or_out;
LED[4]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[4] = DFFE(LED[4]_reg_input, GLOBAL(WEn), , , LED[4]_p3_out);
--LED[3] is LED[3]
LED[3]_or_out = A1L85;
LED[3]_reg_input = LED[3]_or_out;
LED[3]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[3] = DFFE(LED[3]_reg_input, GLOBAL(WEn), , , LED[3]_p3_out);
--LED[2] is LED[2]
LED[2]_or_out = A1L65;
LED[2]_reg_input = LED[2]_or_out;
LED[2]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[2] = DFFE(LED[2]_reg_input, GLOBAL(WEn), , , LED[2]_p3_out);
--LED[1] is LED[1]
LED[1]_or_out = A1L45;
LED[1]_reg_input = LED[1]_or_out;
LED[1]_p3_out = DSP_RSTn & !DSP_ADDR[2] & DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
LED[1] = DFFE(LED[1]_reg_input, GLOBAL(WEn), , , LED[1]_p3_out);
--DREG[7] is DREG[7]
DREG[7]_or_out = !A1L86;
DREG[7]_reg_input = DREG[7]_or_out;
DREG[7]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[7] = DFFE(DREG[7]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[7]_p3_out);
--DREG[6] is DREG[6]
DREG[6]_or_out = !A1L66;
DREG[6]_reg_input = DREG[6]_or_out;
DREG[6]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[6] = DFFE(DREG[6]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[6]_p3_out);
--DREG[5] is DREG[5]
DREG[5]_or_out = !A1L46;
DREG[5]_reg_input = DREG[5]_or_out;
DREG[5]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[5] = DFFE(DREG[5]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[5]_p3_out);
--DREG[4] is DREG[4]
DREG[4]_or_out = !A1L26;
DREG[4]_reg_input = DREG[4]_or_out;
DREG[4]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[4] = DFFE(DREG[4]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[4]_p3_out);
--DREG[3] is DREG[3]
DREG[3]_or_out = !A1L06;
DREG[3]_reg_input = DREG[3]_or_out;
DREG[3]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[3] = DFFE(DREG[3]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[3]_p3_out);
--DREG[2] is DREG[2]
DREG[2]_or_out = !A1L85;
DREG[2]_reg_input = DREG[2]_or_out;
DREG[2]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[2] = DFFE(DREG[2]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[2]_p3_out);
--DREG[1] is DREG[1]
DREG[1]_or_out = !A1L65;
DREG[1]_reg_input = DREG[1]_or_out;
DREG[1]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[1] = DFFE(DREG[1]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[1]_p3_out);
--DREG[0] is DREG[0]
DREG[0]_or_out = !A1L45;
DREG[0]_reg_input = DREG[0]_or_out;
DREG[0]_p3_out = DSP_ADDR[2] & !DSP_ADDR[1] & !DSP_ADDR[4] & !DSP_ADDR[3] & !CS0AND1n & !DSP_ADDR[7] & !DSP_ADDR[5] & !DSP_ADDR[6];
DREG[0] = DFFE(DREG[0]_reg_input, GLOBAL(WEn), DSP_RSTn, , DREG[0]_p3_out);
--A1L22 is CPLD_SDA~3
A1L22_or_out = A1L12;
A1L22 = A1L22_or_out;
--A1L61 is CPLD_NFCE$latch~10
A1L61_p1_out = A1L71 & A1L071;
A1L61_p2_out = A1L61 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L961;
A1L61_p3_out = A1L61 & A1L71;
A1L61_or_out = A1L61_p1_out # A1L61_p2_out # A1L61_p3_out;
A1L61 = A1L61_or_out;
--A1L031 is MY485_CSn$latch~10
A1L031_p1_out = A1L761 & A1L271;
A1L031_p2_out = A1L031 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L871;
A1L031_p3_out = A1L031 & A1L761;
A1L031_or_out = A1L031_p1_out # A1L031_p2_out # A1L031_p3_out;
A1L031 = A1L031_or_out;
--A1L621 is LED_CSn$latch~10
A1L621_p0_out = A1L171 & !DREG[6];
A1L621_p1_out = SPI_CS & A1L171;
A1L621_p2_out = A1L621 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L771;
A1L621_p3_out = A1L621 & SPI_CS;
A1L621_p4_out = A1L171 & !DREG[7];
A1L621_or_out = A1L721 # A1L621_p0_out # A1L621_p1_out # A1L621_p2_out # A1L621_p3_out # A1L621_p4_out;
A1L621 = A1L621_or_out;
--A1L231 is M_CSn$latch~10
A1L231_p0_out = A1L371 & !DREG[6];
A1L231_p1_out = SPI_CS & A1L371;
A1L231_p2_out = A1L231 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L971;
A1L231_p3_out = A1L231 & SPI_CS;
A1L231_p4_out = A1L371 & !DREG[7];
A1L231_or_out = A1L331 # A1L231_p0_out # A1L231_p1_out # A1L231_p2_out # A1L231_p3_out # A1L231_p4_out;
A1L231 = A1L231_or_out;
--A1L72 is DAFSn$latch~10
A1L72_p0_out = A1L471 & !DREG[6];
A1L72_p1_out = SPI_CS & A1L471;
A1L72_p2_out = A1L72 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L081;
A1L72_p3_out = A1L72 & SPI_CS;
A1L72_p4_out = A1L471 & !DREG[7];
A1L72_or_out = A1L82 # A1L72_p0_out # A1L72_p1_out # A1L72_p2_out # A1L72_p3_out # A1L72_p4_out;
A1L72 = A1L72_or_out;
--A1L141 is SDSPI_CSn$latch~10
A1L141_p0_out = A1L571 & !DREG[6];
A1L141_p1_out = SPI_CS & A1L571;
A1L141_p2_out = A1L141 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L181;
A1L141_p3_out = A1L141 & SPI_CS;
A1L141_p4_out = A1L571 & !DREG[7];
A1L141_or_out = A1L241 # A1L141_p0_out # A1L141_p1_out # A1L141_p2_out # A1L141_p3_out # A1L141_p4_out;
A1L141 = A1L141_or_out;
--A1L2 is AICCSn$latch~10
A1L2_p0_out = A1L671 & !DREG[6];
A1L2_p1_out = SPI_CS & A1L671;
A1L2_p2_out = A1L2 & DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L281;
A1L2_p3_out = A1L2 & SPI_CS;
A1L2_p4_out = A1L671 & !DREG[7];
A1L2_or_out = A1L3 # A1L2_p0_out # A1L2_p1_out # A1L2_p2_out # A1L2_p3_out # A1L2_p4_out;
A1L2 = A1L2_or_out;
--~GND~0 is ~GND~0
~GND~0_or_out = GND;
~GND~0 = ~GND~0_or_out;
--~GND~1 is ~GND~1
~GND~1_or_out = GND;
~GND~1 = ~GND~1_or_out;
--~VCC~0 is ~VCC~0
~VCC~0_or_out = GND;
~VCC~0 = !(~VCC~0_or_out);
--~VCC~1 is ~VCC~1
~VCC~1_or_out = GND;
~VCC~1 = !(~VCC~1_or_out);
--~VCC~2 is ~VCC~2
~VCC~2_or_out = GND;
~VCC~2 = !(~VCC~2_or_out);
--~VCC~3 is ~VCC~3
~VCC~3_or_out = GND;
~VCC~3 = !(~VCC~3_or_out);
--~VCC~4 is ~VCC~4
~VCC~4_or_out = GND;
~VCC~4 = !(~VCC~4_or_out);
--~VCC~5 is ~VCC~5
~VCC~5_or_out = GND;
~VCC~5 = !(~VCC~5_or_out);
--~VCC~6 is ~VCC~6
~VCC~6_or_out = GND;
~VCC~6 = !(~VCC~6_or_out);
--~VCC~7 is ~VCC~7
~VCC~7_or_out = GND;
~VCC~7 = !(~VCC~7_or_out);
--~VCC~8 is ~VCC~8
~VCC~8_or_out = GND;
~VCC~8 = !(~VCC~8_or_out);
--~VCC~9 is ~VCC~9
~VCC~9_or_out = GND;
~VCC~9 = !(~VCC~9_or_out);
--~GND~2 is ~GND~2
~GND~2_or_out = GND;
~GND~2 = ~GND~2_or_out;
--~GND~3 is ~GND~3
~GND~3_or_out = GND;
~GND~3 = ~GND~3_or_out;
--~VCC~10 is ~VCC~10
~VCC~10_or_out = GND;
~VCC~10 = !(~VCC~10_or_out);
--~VCC~11 is ~VCC~11
~VCC~11_or_out = GND;
~VCC~11 = !(~VCC~11_or_out);
--~VCC~12 is ~VCC~12
~VCC~12_or_out = GND;
~VCC~12 = !(~VCC~12_or_out);
--~VCC~13 is ~VCC~13
~VCC~13_or_out = GND;
~VCC~13 = !(~VCC~13_or_out);
--~VCC~14 is ~VCC~14
~VCC~14_or_out = GND;
~VCC~14 = !(~VCC~14_or_out);
--~VCC~15 is ~VCC~15
~VCC~15_or_out = GND;
~VCC~15 = !(~VCC~15_or_out);
--~VCC~16 is ~VCC~16
~VCC~16_or_out = GND;
~VCC~16 = !(~VCC~16_or_out);
--~VCC~17 is ~VCC~17
~VCC~17_or_out = GND;
~VCC~17 = !(~VCC~17_or_out);
--~VCC~18 is ~VCC~18
~VCC~18_or_out = GND;
~VCC~18 = !(~VCC~18_or_out);
--~VCC~19 is ~VCC~19
~VCC~19_or_out = GND;
~VCC~19 = !(~VCC~19_or_out);
--~VCC~20 is ~VCC~20
~VCC~20_or_out = GND;
~VCC~20 = !(~VCC~20_or_out);
--~VCC~21 is ~VCC~21
~VCC~21_or_out = GND;
~VCC~21 = !(~VCC~21_or_out);
--~VCC~22 is ~VCC~22
~VCC~22_or_out = GND;
~VCC~22 = !(~VCC~22_or_out);
--~VCC~23 is ~VCC~23
~VCC~23_or_out = GND;
~VCC~23 = !(~VCC~23_or_out);
--~VCC~24 is ~VCC~24
~VCC~24_or_out = GND;
~VCC~24 = !(~VCC~24_or_out);
--~VCC~25 is ~VCC~25
~VCC~25_or_out = GND;
~VCC~25 = !(~VCC~25_or_out);
--~VCC~26 is ~VCC~26
~VCC~26_or_out = GND;
~VCC~26 = !(~VCC~26_or_out);
--~VCC~27 is ~VCC~27
~VCC~27_or_out = GND;
~VCC~27 = !(~VCC~27_or_out);
--A1L761 is reduce_nor~50sexp
A1L761 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3]);
--A1L861 is reduce_nor~54sexp
A1L861 = EXP(!DREG[0] & !DREG[2] & !DREG[1]);
--A1L71 is CPLD_NFCE~9sexp
A1L71 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L861);
--A1L961 is reduce_nor~56sexp
A1L961 = EXP(!DREG[2] & !DREG[1]);
--A1L071 is reduce_or~528sexp
A1L071 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L961);
--A1L771 is reduce_or~537sexp
A1L771 = EXP(DREG[0] & DREG[2] & DREG[1]);
--A1L171 is reduce_or~529sexp
A1L171 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L771);
--A1L871 is reduce_or~541sexp
A1L871 = EXP(!DREG[0] & DREG[2] & DREG[1]);
--A1L271 is reduce_or~530sexp
A1L271 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L871);
--A1L971 is reduce_or~545sexp
A1L971 = EXP(DREG[0] & DREG[2] & !DREG[1]);
--A1L371 is reduce_or~531sexp
A1L371 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L971);
--A1L081 is reduce_or~549sexp
A1L081 = EXP(!DREG[0] & DREG[2] & !DREG[1]);
--A1L471 is reduce_or~532sexp
A1L471 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L081);
--A1L181 is reduce_or~553sexp
A1L181 = EXP(DREG[0] & !DREG[2] & DREG[1]);
--A1L571 is reduce_or~533sexp
A1L571 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L181);
--A1L281 is reduce_or~557sexp
A1L281 = EXP(!DREG[0] & !DREG[2] & DREG[1]);
--A1L671 is reduce_or~534sexp
A1L671 = EXP(DREG[7] & DREG[6] & DREG[5] & DREG[4] & DREG[3] & A1L281);
--A1L721 is LED_CSn$latch~22
A1L721_p0_out = A1L621 & !DREG[6];
A1L721_p1_out = !DREG[5] & A1L171;
A1L721_p2_out = A1L171 & !DREG[4];
A1L721_p3_out = A1L171 & !DREG[3];
A1L721_p4_out = !DREG[7] & A1L621;
A1L721 = A1L821 # A1L721_p0_out # A1L721_p1_out # A1L721_p2_out # A1L721_p3_out # A1L721_p4_out;
--A1L821 is LED_CSn$latch~23
A1L821_p1_out = !DREG[5] & A1L621;
A1L821_p2_out = A1L621 & !DREG[4];
A1L821_p3_out = A1L621 & !DREG[3];
A1L821 = A1L821_p1_out # A1L821_p2_out # A1L821_p3_out;
--A1L331 is M_CSn$latch~22
A1L331_p0_out = A1L231 & !DREG[6];
A1L331_p1_out = !DREG[5] & A1L371;
A1L331_p2_out = A1L371 & !DREG[4];
A1L331_p3_out = A1L371 & !DREG[3];
A1L331_p4_out = !DREG[7] & A1L231;
A1L331 = A1L431 # A1L331_p0_out # A1L331_p1_out # A1L331_p2_out # A1L331_p3_out # A1L331_p4_out;
--A1L431 is M_CSn$latch~23
A1L431_p1_out = !DREG[5] & A1L231;
A1L431_p2_out = A1L231 & !DREG[4];
A1L431_p3_out = A1L231 & !DREG[3];
A1L431 = A1L431_p1_out # A1L431_p2_out # A1L431_p3_out;
--A1L82 is DAFSn$latch~22
A1L82_p0_out = A1L72 & !DREG[6];
A1L82_p1_out = !DREG[5] & A1L471;
A1L82_p2_out = A1L471 & !DREG[4];
A1L82_p3_out = A1L471 & !DREG[3];
A1L82_p4_out = !DREG[7] & A1L72;
A1L82 = A1L92 # A1L82_p0_out # A1L82_p1_out # A1L82_p2_out # A1L82_p3_out # A1L82_p4_out;
--A1L92 is DAFSn$latch~23
A1L92_p1_out = !DREG[5] & A1L72;
A1L92_p2_out = A1L72 & !DREG[4];
A1L92_p3_out = A1L72 & !DREG[3];
A1L92 = A1L92_p1_out # A1L92_p2_out # A1L92_p3_out;
--A1L241 is SDSPI_CSn$latch~22
A1L241_p0_out = A1L141 & !DREG[6];
A1L241_p1_out = !DREG[5] & A1L571;
A1L241_p2_out = A1L571 & !DREG[4];
A1L241_p3_out = A1L571 & !DREG[3];
A1L241_p4_out = !DREG[7] & A1L141;
A1L241 = A1L341 # A1L241_p0_out # A1L241_p1_out # A1L241_p2_out # A1L241_p3_out # A1L241_p4_out;
--A1L341 is SDSPI_CSn$latch~23
A1L341_p1_out = !DREG[5] & A1L141;
A1L341_p2_out = A1L141 & !DREG[4];
A1L341_p3_out = A1L141 & !DREG[3];
A1L341 = A1L341_p1_out # A1L341_p2_out # A1L341_p3_out;
--A1L3 is AICCSn$latch~22
A1L3_p0_out = A1L2 & !DREG[6];
A1L3_p1_out = !DREG[5] & A1L671;
A1L3_p2_out = A1L671 & !DREG[4];
A1L3_p3_out = A1L671 & !DREG[3];
A1L3_p4_out = !DREG[7] & A1L2;
A1L3 = A1L4 # A1L3_p0_out # A1L3_p1_out # A1L3_p2_out # A1L3_p3_out # A1L3_p4_out;
--A1L4 is AICCSn$latch~23
A1L4_p1_out = !DREG[5] & A1L2;
A1L4_p2_out = A1L2 & !DREG[4];
A1L4_p3_out = A1L2 & !DREG[3];
A1L4 = A1L4_p1_out # A1L4_p2_out # A1L4_p3_out;
--DSP_RSTn is DSP_RSTn
--operation mode is input
DSP_RSTn = INPUT();
--DSPCLK_OUT is DSPCLK_OUT
--operation mode is input
DSPCLK_OUT = INPUT();
--R_Wn is R_Wn
--operation mode is input
R_Wn = INPUT();
--RDn is RDn
--operation mode is input
RDn = INPUT();
--WEn is WEn
--operation mode is input
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