mydsp2812.map.rpt

DSP2812 TFT彩屏显示 源码 给你得嵌入式系统增加TFT彩屏

+----------------------------+------------+------+---------------------+--------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+------------+------+---------------------+--------------+
; |MYDSP2812                 ; 74         ; 92   ; |MYDSP2812          ; work         ;
+----------------------------+------------+------+---------------------+--------------+


+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches                                                               ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name                                         ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; CPLD_NFCE$latch                                    ; WideOr8             ; yes                    ;
; LED_CSn$latch                                      ; WideOr1             ; yes                    ;
; MY485_CSn$latch                                    ; WideOr2             ; yes                    ;
; M_CSn$latch                                        ; WideOr3             ; yes                    ;
; DAFSn$latch                                        ; WideOr4             ; yes                    ;
; SDSPI_CSn$latch                                    ; WideOr5             ; yes                    ;
; AICCSn$latch                                       ; WideOr6             ; yes                    ;
; Number of user-specified and inferred latches = 7  ;                     ;                        ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
    Info: Processing started: Fri Apr 25 13:40:02 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off MYDSP2812 -c MYDSP2812
Info: Found 1 design units, including 1 entities, in source file MYDSP2812.v
    Info: Found entity 1: MYDSP2812
Info: Elaborating entity "MYDSP2812" for the top level hierarchy
Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(191): variable "SPI_CS" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(193): variable "SPI_CS" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(194): variable "SPI_CS" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(195): variable "SPI_CS" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10235): Verilog HDL Always Construct warning at MYDSP2812.v(196): variable "SPI_CS" is read inside the Always Construct but isn't in the Always Construct's Event Control
Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable "LED_CSn", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable "MY485_CSn", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable "M_CSn", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable "DAFSn", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable "SDSPI_CSn", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable "AICCSn", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at MYDSP2812.v(189): inferring latch(es) for variable "CPLD_NFCE", which holds its previous value in one or more paths through the always construct
Warning (10034): Output port "NMI" at MYDSP2812.v(66) has no driver
Warning (10034): Output port "INT2" at MYDSP2812.v(68) has no driver
Info (10041): Inferred latch for "CPLD_NFCE" at MYDSP2812.v(189)
Info (10041): Inferred latch for "AICCSn" at MYDSP2812.v(189)
Info (10041): Inferred latch for "SDSPI_CSn" at MYDSP2812.v(189)
Info (10041): Inferred latch for "DAFSn" at MYDSP2812.v(189)
Info (10041): Inferred latch for "M_CSn" at MYDSP2812.v(189)
Info (10041): Inferred latch for "MY485_CSn" at MYDSP2812.v(189)
Info (10041): Inferred latch for "LED_CSn" at MYDSP2812.v(189)
Warning (10665): Bidirectional port "SPI_SIMO" at MYDSP2812.v(76) has a one-way connection to bidirectional port "CPLDSPI_SIMO"
Warning (10665): Bidirectional port "CPLD_SDA" at MYDSP2812.v(82) has a one-way connection to bidirectional port "GPIOB[14]"
Warning: The bidir "SPI_SOMI" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IFCLK" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[9]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[10]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[11]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[12]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[13]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "IOPORT[14]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "DSP_DATA[0]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "DSP_DATA[1]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "DSP_DATA[2]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "DSP_DATA[3]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "DSP_DATA[4]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "DSP_DATA[5]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "DSP_DATA[6]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "DSP_DATA[7]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIOB[8]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "GPIOB[9]" has no source; inserted an always disabled tri-state buffer.
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIOB[10]~5 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIOB[11]~4 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIOB[12]~3 that it feeds
Warning: Inserted an always-enabled tri-state buffer between logic and the tri-state bus GPIOB[13]~2 that it feeds
Warning: The bidir "GPIOB[15]" has no source; inserted an always disabled tri-state buffer.
Warning: The bidir "SPI_SIMO" has no source; inserted an always disabled tri-state buffer.
Info: Registers with preset signals will power-up high
Warning: TRI or OPNDRN buffers permanently enabled
    Warning: Node "GPIOB[10]~15"
    Warning: Node "GPIOB[11]~16"
    Warning: Node "GPIOB[12]~17"
    Warning: Node "GPIOB[13]~18"
    Warning: Node "GPB~0"
    Warning: Node "CPLDSPI_SIMO~2"
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "NMI" stuck at GND
    Warning (13410): Pin "INT2" stuck at GND
    Warning (13410): Pin "CPLD_FALE" stuck at VCC
    Warning (13410): Pin "CPLD_FCLE" stuck at VCC
    Warning (13410): Pin "DACSn" stuck at GND
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin "WEn" to global clock signal
Warning: Output pin "CPLD_SCL" driven by bidirectional pin "GPIOB[8]" not tri-stated
Warning: Design contains 4 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "DSPCLK_OUT"
    Warning (15610): No output dependent on input pin "R_Wn"
    Warning (15610): No output dependent on input pin "READY"
    Warning (15610): No output dependent on input pin "USB_FLAGA"
Info: Implemented 179 device resources after synthesis - the final resource count might be different
    Info: Implemented 26 input pins
    Info: Implemented 31 output pins
    Info: Implemented 35 bidirectional pins
    Info: Implemented 74 macrocells
    Info: Implemented 13 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 67 warnings
    Info: Allocated 142 megabytes of memory during processing
    Info: Processing ended: Fri Apr 25 13:40:05 2008
    Info: Elapsed time: 00:00:03