adc_lpc915.a51

简易虚拟示波器（只测波形不测值）之单片机端汇编程序（LPC915)

;************************ LPC915 **********************************************
;------------------------------------------------------------------------------
;  This file is part of the C51 Compiler package
;  Startup Code for the Philips LPC9xx devices 
;  Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.
;------------------------------------------------------------------------------
;  START900.A51:  This code is executed after processor reset.
;  You may add this file to a uVision2 project.
;
;  To translate this file use Ax51 with the following invocation:
;
;     Ax51 START900.A51
;
;  To link the modified START900.OBJ file to your application use the following
;  Lx51 invocation:
;
;     Lx51 <your object file list>, START900.OBJ <controls>
;
;------------------------------------------------------------------------------
;
;  User-defined Power-On Initialization of Memory
;
;  With the following EQU statements the initialization of memory
;  at processor reset can be defined:
;
;               ; the absolute start-address of IDATA memory is always 0
;IDATALEN        EQU     100H    ; the length of IDATA memory in bytes.
;
;XDATASTART      EQU     0H      ; the absolute start-address of XDATA memory
;XDATALEN        EQU     0H      ; the length of XDATA memory in bytes.
;
;  Notes:  The IDAT A space overlaps physically the DATA and BIT areas of the
;          LPC9xx device.
;
;------------------------------------------------------------------------------
;
;  Reentrant Stack Initilization
;
;  The following EQU statements define the stack pointer for reentrant
;  functions and initialized it:
;
;  Stack Space for reentrant functions in the SMALL model.
;IBPSTACK        EQU     0       ; set to 1 if small reentrant is used.
;IBPSTACKTOP     EQU     01FH+1  ; set top of stack to highest location+1.
;
;  Stack Space for reentrant functions in the LARGE model.      
;XBPSTACK        EQU     0       ; set to 1 if large reentrant is used.
;XBPSTACKTOP     EQU     0FFH+1 ; set top of stack to highest location+1.
;
;  Stack Space for reentrant functions in the COMPACT model.    
;PBPSTACK        EQU     0       ; set to 1 if compact reentrant is used.
;PBPSTACKTOP     EQU     0FFH+1  ; set top of stack to highest location+1.
;
;------------------------------------------------------------------------------
;
;  Setup LPC9xx Configuration Register (UCFG1, BOOTVEC, BOOTSTAT, SEC0..SEC7)
;
; Oscillator Configuration (UCFG1.0 .. UCFG1.2)
; FOSC       Val  Description
; ----       ---  -----------
FOSC EQU 0  ; 0 = high frequency crystal or resonator (4MHz .. 20MHz)
;           ; 1 = medium frequency crystal or resonator (100kHz .. 4MHz)
;           ; 2 = low frequency crystal (20kHz .. 100kHz)
;           ; 3 = internal RC oscillator (7.373MHz +/- 2.5%) (default on unprogrammed part)
;           ; 4 = internal Watchdog oscillator (400kHz +20/-30%)
;           ; 7 = external clock input on X1
;
; Watchdog Saftey Enable (UCFG1.4)
; WDSE       Val  Description
; ----       ---  -----------
WDSE EQU 0  ; 0 = user can set WDCLK to select clock source(default on unprogrammed part) 
;           ; 1 = Always use WDCLK, WDCON and WDL can be written once, WDT is always running 
;
; Brownout Detect Enable (UCFG1.5)
; BOE       Val  Description
; ----       ---  -----------
BOE EQU 1   ; 0 = 
;           ; 1 = (default on unprogrammed part) 
;
; Reset PIN disable (UCFG1.6)
; RPD        Val  Description
; ---        ---  -----------
RPD  EQU 1  ; 0 = P1.5 will act as reset pin (low active)
;           ; 1 = P1.5 can be used as input PIN (default on unprogrammed part)
;           
; Watchdog timer enable (UCFG1.7)
; WDTE       Val  Description
; ----       ---  -----------
WDTE EQU 0  ; 0 = watchdog disabled WDSE has no effect (default on unprogrammed part)
;           ; 1 = watchdog enabled
;
; BOOTVECTOR (BOOTVEC)
; BOOTVEC    Val  Description
; ----       ---  -----------
;BOOTVEC EQU 0x1F  ; points to ISP entry point (default on unprogrammed part)
;程序开始后检测某一脚，电高为低则跳到0x1F,enter point 0x1F00
BOOTVEC EQU 0
;
; BOOTSTATUS (BOOTSTAT)
; BOOTSTAT   Val  Description
; ----       ---  -----------
;BOOTSTAT EQU 0x01 ; enables ISP entry on power-up (default on unprogrammed part)
BOOTSTAT EQU 0
;
; Flash Security Configuration (SEC0.0 .. SEC0.2)
; SEC0       Val  Description
; ----       ---  -----------
SEC0 EQU 0  ; 0 = no security on sector 0 (default on unprogrammed part)
;           ; 1 = MOVC disabled on sector 0
;           ; 2 = program/erase disabled on sector 0
;           ; 3 = MOVC disabled, program/erase disabled on sector 0 
;           ; 4 = IAP/ISP global erase disabled on sector 0
;           ; 5 = MOVC disabled, IAP/ISP global erase disabled on sector 0
;           ; 6 = program/erase disabled, IAP/ISP global erase disabled on sector 0
;           ; 7 = MOVC disabled, program/erase disabled, IAP/ISP global erase disabled on sector 0
SEC1 EQU 0
SEC2 EQU 0
SEC3 EQU 0
SEC4 EQU 0
SEC5 EQU 0
SEC6 EQU 0
SEC7 EQU 0

;#include "LPC915SFR.H"
 P0   data 0x80
 P1   data 0x90
 P2   data 0xA0
 P3   data 0xB0
 PSW  data 0xD0
 ACC  data 0xE0
 B    data 0xF0
 SP   data 0x81
 DPL  data 0x82
 DPH  data 0x83
 PCON data 0x87
 TCON data 0x88
 TMOD data 0x89
 TL0  data 0x8A
 TL1  data 0x8B
 TH0  data 0x8C
 TH1  data 0x8D
 IEN0 data 0xA8
 IP0  data 0xB8
 SCON data 0x98
 SBUF data 0x99
 ADCON0 data 0x8E
 ADCON1 data 0x97
 ADMODA data 0xC0
 ADMODB data 0xA1
 ADINS  data 0xA3
 AD0DAT0 data 0xC5
 AD0DAT1 data 0xC6
 AD0DAT2 data 0xC7
 AD0DAT3 data 0xF4
 AD1DAT0 data 0xD5
 AD1DAT1 data 0xD6
 AD1DAT2 data 0xD7
 AD1DAT3 data 0xF5
 AD0BH  data 0xBB
 AD0BL  data 0xA6
 AD1BH  data 0xC4
 AD1BL  data 0xBC
 AUXR1  data 0xA2
 SADDR  data 0xA9
 SADEN  data 0xB9
 TL2    data 0xCC
 TH2    data 0xCD
 BRGR0  data 0xBE
 BRGR1  data 0xBF
 BRGCON data 0xBD
 CCCRA  data 0xEA
 CCCRB  data 0xEB
 CCCRC  data 0xEC
 CCCRD  data 0xED
 CMP1   data 0xAC
 CMP2   data 0xAD
 DEECON data 0xF1
 DEEDAT data 0xF2
 DEEADR data 0xF3
 DIVM   data 0x95
 I2ADR  data 0xDB
 I2CON  data 0xD8
 I2DAT  data 0xDA
 I2SCLH data 0xDD
 I2SCLL data 0xDC
 I2STAT data 0xD9
 ICRAH  data 0xAB
 ICRAL  data 0xAA
 ICRBH  data 0xAF
 ICRBL  data 0xAE
 IEN1   data 0xE8
 IP1    data 0xF8
 IP1H   data 0xF7
 KBCON  data 0x94
 KBMASK data 0x86
 KBPATN data 0x93
 OCRAH  data 0xEF
 OCRAL  data 0xEE
 OCRBH  data 0xFB
 OCRBL  data 0xFA
 OCRCH  data 0xFD
 OCRCL  data 0xFC
 OCRDH  data 0xFF
 OCRDL  data 0xFE
 P0M1   data 0x84
 P0M2   data 0x85
 P1M1   data 0x91
 P1M2   data 0x92
 P2M1   data 0xA4
 P2M2   data 0xA5
 P3M1   data 0xB1
 P3M2   data 0xB2
 PCONA  data 0xB5
 PT0AD  data 0xF6
 RSTSRC data 0xDF
 RTCCON data 0xD1
 RTCH   data 0xD2
 RTCL   data 0xD3
 SSTAT  data 0xBA
 SPCTL  data 0xE2
 SPSTAT data 0xE1
 SPDAT  data 0xE3
 TAMOD  data 0x8F
 TCR20  data 0xC8
 TCR21  data 0xF9
 TICR2  data 0xC9
 TIFR2  data 0xE9
 TISE2  data 0xDE
 TOR2H  data 0xCF
 TOR2L  data 0xCE
 TPCR2H data 0xCB
 TPCR2L data 0xCA
 TRIM   data 0x96
 WDCON  data 0xA7
 WDL    data 0xC1
 WFEED1 data 0xC2
 WFEED2 data 0xC3
 IP0H   data 0xB7

/*  BIT Registers  */
/*  PSW   */
 CY   bit PSW.7
 AC   bit PSW.6
 F0   bit PSW.5
 RS1  bit PSW.4
 RS0  bit PSW.3
 OV   bit PSW.2
 F1   bit PSW.1
 P    bit PSW.0

/*  AUXR1   */
/*
CLKLP bit AUXR1.7
 EBRR  bit AUXR1.6
 ENT1  bit AUXR1.5
 ENT0  bit AUXR1.4
 SRSt  bit AUXR1.3
 DPS   bit AUXR1.0
*/

/*  TCON  */
 TF1  bit TCON.7
 TR1  bit TCON.6
 TF0  bit TCON.5
 TR0  bit TCON.4
 IE1  bit TCON.3
 IT1  bit TCON.2
 IE0  bit TCON.1
 IT0  bit TCON.0

/*  IEN0   */
 EA   bit IEN0.7
 EWDRT bit IEN0.6
 EBO   bit IEN0.5
 ES   bit IEN0.4 ; alternatively "ESR"
 ESR  bit IEN0.4
 ET1  bit IEN0.3
 EX1  bit IEN0.2
 ET0  bit IEN0.1
 EX0  bit IEN0.0

/*  IEN1   */
 EAD  bit IEN1.7 ; alternatively "EIEE" 
 EST  bit IEN1.6
 ECCU bit IEN1.4
 ESPI bit IEN1.3
 EC   bit IEN1.2
 EKBI bit IEN1.1
 EI2C bit IEN1.0

/*  IP0   */ 
 PWDRT bit IP0.6
 PB0   bit IP0.5
 PS    bit IP0.4 ; alternatively "PSR"
 PSR   bit IP0.4
 PT1   bit IP0.3
 PX1   bit IP0.2
 PT0   bit IP0.1
 PX0   bit IP0.0

/*  IP1   */
 PAD  bit IP1.7 ; alternatively "PIEE" 
 PST  bit IP1.6
 PCCU bit IP1.4
 PSPI bit IP1.3
 PC_C   bit IP1.2
 PKBI bit IP1.1
 PI2C bit IP1.0

/*  SCON  */
 SM0  bit SCON.7 ; alternatively "FE"
 FE   bit SCON.7
 SM1  bit SCON.6
 SM2  bit SCON.5
 REN  bit SCON.4
 TB8  bit SCON.3
 RB8  bit SCON.2
 TI   bit SCON.1
 RI   bit SCON.0

/*  I2CON  */
 I2EN  bit I2CON.6
 STA   bit I2CON.5
 STO   bit I2CON.4
 SI    bit I2CON.3
 AA    bit I2CON.2
 CRSEL bit I2CON.0

/*  P0  */
 KB7 bit P0.7 ; alternatively "T1"
 T1 bit P0.7
 KB6 bit P0.6 ; alternatively "CMP1"
; CMP1 bit P0.6
 KB5 bit P0.5
 KB4 bit P0.4
 KB3 bit P0.3
 KB2 bit P0.2
 KB1 bit P0.1
 KB0 bit P0.0 ; alternatively "CMP2"
; CMP2 bit P0.0

/*  P1  */
 OCC     bit P1.7
 OCB     bit P1.6
 RST     bit P1.5
 INT1    bit P1.4
 INT0    bit P1.3 ; alternatively "SDA"
 SDA     bit P1.3
 T0      bit P1.2 ; alternatively "SCL"
 SCL     bit P1.2
 RxD     bit P1.1
 TxD     bit P1.0

/*  P2  */
 ICA     bit P2.7
 OCA     bit P2.6
 SPICLK  bit P2.5
 SS      bit P2.4
 MISO    bit P2.3
 MOSI    bit P2.2
 OCD     bit P2.1
 ICB     bit P2.0

/*  P3  */
 XTAL1 bit P3.1
 XTAL2 bit P3.0

/* TCR20 */
 PLLEN bit TCR20.7
 HLTRN bit TCR20.6
 HLTEN bit TCR20.5
 ALTCD bit TCR20.4
 ALTAB bit TCR20.3
 TDIR2 bit TCR20.2
 TMOD21 bit TCR20.1
 TMOD20 bit TCR20.0

/* ADMODA */
 BNDI1  bit ADMODA.7
 BURST1 bit ADMODA.6
 SCC1   bit ADMODA.5
 SCAN1  bit ADMODA.4
 BNDI0  bit ADMODA.3
 BURST0 bit ADMODA.2
 SCC0   bit ADMODA.1
 SCAN0  bit ADMODA.0

;2006.12.14 add one stop bit for RECIVE DATA
;***************** USER DATA ***********************
;********************************* SEND BYTE 使用奇校验***************
;R1 USE FOR P_TX_E
timer0_H data 29h