sfr_7546.h

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/*------------------------------------------------------
   Capture Output Mode Register (0021H)	
------------------------------------------------------*/
bit CMP0PL		= CMOM.0;		/* Capture 0 Output Level Latch */
bit CMP1PL		= CMOM.1;		/* Capture 1 Output Level Latch */
bit CMP2PL		= CMOM.2;		/* Capture 2 Output Level Latch */
bit CMP3PL		= CMOM.3;		/* Capture 3 Output Level Latch */
bit CMP0TG		= CMOM.4;		/* Compare 0 Trigger Enable Bit */
bit CMP1TG		= CMOM.5;		/* Compare 1 Trigger Enable Bit */
bit CMP2TG		= CMOM.6;		/* Compare 2 Trigger Enable Bit */
bit CMP3TG		= CMOM.7;		/* Compare 3 Trigger Enable Bit */

/*------------------------------------------------------
   Capture/Comare Status Register (0022H)
------------------------------------------------------*/
bit CMP0STS		= CCSR.0;		/* Compare 0 Output  Status Bit */
bit CMP1STS		= CCSR.1;		/* Compare 1 Output  Status Bit */
bit CMP2STS		= CCSR.2;		/* Compare 2 Output  Status Bit */
bit CMP3STS		= CCSR.3;		/* Compare 3 Output  Status Bit */
bit CAP0STS		= CCSR.4;		/* Capture 0 Status Bit */
bit CAP1STS		= CCSR.5;		/* Capture 1 Status Bit */

/*------------------------------------------------------
    Compare Interrupt Source Set Register (0023H)
------------------------------------------------------*/
bit CL00IS		= CISR.0;		/* Compare Latch 00 Interrupt Source Bit */
bit CL01IS		= CISR.1;		/* Compare Latch 01 Interrupt Source Bit */
bit CL10IS		= CISR.2;		/* Compare Latch 10 Interrupt Source Bit */
bit CL11IS		= CISR.3;		/* Compare Latch 11 Interrupt Source Bit */
bit CL20IS		= CISR.4;		/* Compare Latch 20 Interrupt Source Bit */
bit CL21IS		= CISR.5;		/* Compare Latch 21 Interrupt Source Bit */
bit CL30IS		= CISR.6;		/* Compare Latch 30 Interrupt Source Bit */
bit CL31IS		= CISR.7;		/* Compare Latch 31 Interrupt Source Bit */

/*------------------------------------------------------
   Timer Count Source Set Register (002AH)
------------------------------------------------------*/
bit TXCK0		= TCSS.0;		/* Timer X Count Source Selection Bit s(0,1) */
bit TXCK1		= TCSS.1;		/* */
bit TACK0		= TCSS.2;		/* Timer A Count Source Selection Bit s(2-4) */
bit TACK1		= TCSS.3;		/* */
bit TACK2		= TCSS.4;		/* */
bit TBCK0		= TCSS.5;		/* Timer B Count Source Selection Bit s(5-7) */
bit TBCK1		= TCSS.6;		/* */
bit TBCK2		= TCSS.7;		/* */

/*------------------------------------------------------
   TimerX mode Register (002BH)
------------------------------------------------------*/
bit TXMOD0		= TXM.0;		/* TimerX Oprating Mode Bit s(0,1) */
bit TXM0D1		= TXM.1;		/* */
bit R0EDG		= TXM.2;		/* CNTR0 Active Edge Switch Bit */
bit TXSTP		= TXM.3;		/* TimerX Count Stop Bit */
bit TXOCNT		= TXM.4;		/* P03/TXout Output Valid Bit */

/*------------------------------------------------------
    Serial I/O1 status Register (0019H)
------------------------------------------------------*/
bit TBE1		= SIO1STS.0;	/* Transmit Buffer Empty Flag */
bit RBF1		= SIO1STS.1;	/* Receive  Buffer Full Flag */
bit TSC1		= SIO1STS.2;	/* Transmit Shift Completion Flag */
bit OE1			= SIO1STS.3;	/* Overrun Error Flag */
bit PE1			= SIO1STS.4;	/* Parity Error Flag */
bit FE1			= SIO1STS.5;	/* Framing Error Flag */
bit SE1			= SIO1STS.6;	/* Summing Error Flag */

/*------------------------------------------------------
 Serial I/O1 control Register (001AH)
------------------------------------------------------*/
bit CSS1		= SIO1CON.0;	/* BRG count source  selection  Bit */
bit SCS1		= SIO1CON.1;	/* Serial I/O1 synchronous clock selection Bit */
bit SRDY1		= SIO1CON.2;	/* SRDY1 output Enable Bit */
bit TIC1		= SIO1CON.3;	/* Transmit Interrupt source selection Bit */
bit TE1			= SIO1CON.4;	/* Transmit Enable Bit */
bit RE1			= SIO1CON.5;	/* Receive Enable Bit */
bit SIOM1		= SIO1CON.6;	/* Serial I/O1 mode selection Bit */
bit SIOE1		= SIO1CON.7;	/* Serial I/O1 Enable Bit */

/*------------------------------------------------------
 UART1 control Register (001BH)
------------------------------------------------------*/
bit CHAS1		= UART1CON.0;    /* Charactor length selection Bit */
bit PARE1		= UART1CON.1; 	 /* Parity Enable Bit */
bit PARS1		= UART1CON.2;	 /* Parity selection Bit */
bit STPS1		= UART1CON.3;	 /* Stop Bit length selecion Bit */
bit POFF1		= UART1CON.4;	 /* P11/TXD1 P-channel output disable Bit */

/*------------------------------------------------------
  Serial I/O2 status Register (002FH)
------------------------------------------------------*/
bit TBE2		= SIO2STS.0;	/* Transmit Buffer Empty Flag */
bit RBF2		= SIO2STS.1;	/* Receive Buffer Full Flag */
bit TSC2		= SIO2STS.2;	/* Transmit Shift Completion Flag */
bit OE2			= SIO2STS.3;	/* Overrun Error Flag */
bit PE2			= SIO2STS.4;	/* Parity  Error Flag */
bit FE2			= SIO2STS.5;	/* Framing Error Flag */
bit SE2			= SIO2STS.6;	/* Summing Error Flag */

/*------------------------------------------------------
   Serial I/O2 control Register (0030H)	
------------------------------------------------------*/
bit CSS2		= SIO2CON.0;	/* BRG Count Source Selection Bit */
bit SCS2		= SIO2CON.1;	/* Serial I/O1 Synchronous Clock Selection Bit */
bit SRDY2		= SIO2CON.2;	/* SRDY1 Output Enable Bit */
bit TIC2		= SIO2CON.3;	/* Transmit Interrupt Source Selection Bit */
bit TE2			= SIO2CON.4;	/* Transmit Enable Bit */
bit RE2			= SIO2CON.5;	/* Receive Enable Bit */
bit SIOM2		= SIO2CON.6;	/* Serial I/O1 Mode Selection Bit */
bit SIOE2		= SIO2CON.7;	/* Serial I/O1 Enable Bit */

/*------------------------------------------------------
   UART2 control Register (0031H)
------------------------------------------------------*/
bit CHAS2		= UART2CON.0; 	/* Charactor Length Selection Bit */
bit PARE2		= UART2CON.1;	/* Parity Enable Bit */
bit PARS2	 	= UART2CON.2;	/* Parity Selection Bit */
bit STPS2		= UART2CON.3;	/* Stop Bit Length Selecion Bit */

/*------------------------------------------------------
    A/D control Register (0034H)	
------------------------------------------------------*/
bit CH0			= ADCON.0; 		/* Analog Input Pin selection Bit s(0-2) */
bit CH1			= ADCON.1; 		/* */
bit CH2			= ADCON.2; 		/* */
bit CKS			= ADCON.3; 		/* A/D Conversion Clock Selection Bit */
bit ADSTP		= ADCON.4; 		/* A/D Conversion Completion Bit */

/*------------------------------------------------------
   On-chip Oscillation Division Ratio Selection Register (0037H)
------------------------------------------------------*/
bit ROSCSEL0	= RODR.0;		/* On-chip Oscillator Division Ratio */
bit ROSCSEL1	= RODR.1;		/* */

/*------------------------------------------------------
   MISRG (0038H)
------------------------------------------------------*/
bit MISRG0   	= MISRG.0;		/* Oscillation Stabilization Time Set Bit After */
								/* Release Of The STP Instruction */
bit MISRG1   	= MISRG.1;		/* Ceramic or RC oscillation Stop */
								/* Detection Function Active Bit */
bit MISRG2   	= MISRG.2;		/* Oscillation Stop Reset Bit */
bit MISRG3   	= MISRG.3;		/* Oscillation Stop Detection Status Bit */

/*------------------------------------------------------
   Watch Timer Control Register (0039H)
------------------------------------------------------*/
bit STPFS		= WDTCON.6;		/* STP Instruction Function Selection Bit */
bit WHCKSEL		= WDTCON.7;		/* Watchdog Timer H Count Source Selection Bit */

/*------------------------------------------------------
   CPU Mode Register (003BH)
------------------------------------------------------*/
bit CPUMOD0		= CPUM.0;		/* Processor Mode Bit s(0,1) */
bit CPUMOD1		= CPUM.1;		/* */
bit SPSEL		= CPUM.2;		/* Stack Page Selection Bit */
bit ROSCEN		= CPUM.3;		/* On-chip Oscillator Oscillation Control Bit */
bit XINEN		= CPUM.4;		/* XIN Oscillation Control Bit */
bit OSCSEL		= CPUM.5;		/* Oscillation Mode Selection Bit */
bit CPUCK0		= CPUM.6;		/* Clock Division Ratio Selection Bit s(6,7) */
bit CPUCK1		= CPUM.7;		/* */
/*------------------------------------------------------
   Interrupt Edge Select Register (003AH)
------------------------------------------------------*/
bit INT0PL		= INTEDGE.0;	/* INT0 Interrupt Edge Selection Bit */
bit INT1PL		= INTEDGE.1;	/* INT1 Interrupt Edge Selection Bit */
bit INT1SEL		= INTEDGE.2;	/* INT1 input Port Selection Bit */
bit KI0EN		= INTEDGE.5;	/* P00 Key-on Wakeup Enable Bit */
bit KI4EN		= INTEDGE.6;	/* P04 Key-on Wakeup Enable Bit */
bit KI6EN		= INTEDGE.7;	/* P06 Key-on Wakeup Enable Bit */

/*------------------------------------------------------
   Interrupt Source Set Register (000AH)
------------------------------------------------------*/
bit IV_KI	 	= INTSET.0;		/* Key-on Wakeup Interrupt Valid Bit */
bit IV_U1BC 	= INTSET.1;		/* UART1 Bus Collision Interrupt valid Bit */
bit IV_AD	 	= INTSET.2;		/* A/D Conversion Interrupt Valid Bit */
bit IV_T1	 	= INTSET.3;		/* Timer 1 Interrupt Valid Bit */

/*------------------------------------------------------
   Interrupt source discrimination Register (000BH)
------------------------------------------------------*/
bit ID_KI		= INTDIS.0;		/* Key-on Wakeup Interrupt Discrimination Bit */
bit ID_U1BC		= INTDIS.1;		/* UART1 Bus Collision Interrupt Discrimination Bit */
bit ID_AD		= INTDIS.2;		/* A/D Conversion Interrupt Discrimination Bit */
bit ID_T1		= INTDIS.3;		/* Timer1 Interrupt Discrimination Bit */

/*------------------------------------------------------
   Interrupt Request Register1 (003CH)
------------------------------------------------------*/
bit IR_S1R		= IREQ1.0;		/* Serial I/O1 Receive Interrupt Request Bit */	
bit IR_S1T		= IREQ1.1;		/* Serial I/O1 Transmit Interrupt Request Bit */	
bit IR_S2R		= IREQ1.2;		/* Serial I/O2 Receive Interrupt Request Bit */	
bit IR_S2T		= IREQ1.3;		/* Serial I/O2 Transmit Interrupt Request Bit */	
bit IR_INT0		= IREQ1.4;		/* INT0 Interrupt Request Bit */	
bit IR_INT1		= IREQ1.5;		/* INT1 Interrupt Request Bit */	
bit IR_KIU1BC	= IREQ1.6;		/* Key-on Wake Up Interrupt Request Bit */
 								/* UART1 Bus Collision Interrupt Request Bit */
bit IR_CNTR0	= IREQ1.7;		/* CNTR0 Interrupt Request Bit */	

/*------------------------------------------------------
   Interrupt Request Register2 (003DH)
------------------------------------------------------*/
bit IR_CAP0		= IREQ2.0;		/* Capture 0 Interrupt Request Bit */
bit IR_CAP1		= IREQ2.1;		/* Capture 1 Interrupt Request Bit */	
bit IR_CMP		= IREQ2.2;		/* Compare Interrupt Request Bit */
bit IR_TX		= IREQ2.3;		/* Timer X Interrupt Request Bit */	
bit IR_TA		= IREQ2.4;		/* Timer A Interrupt Request Bit */	
bit IR_TB		= IREQ2.5;		/* Timer B Interrupt Request Bit */	
bit IR_ADT1		= IREQ2.6;		/* A/D conversion Interrupt Request Bit */
								/* Timer 1 Interrupt Request Bit */

/*------------------------------------------------------
   Interrupt Control Register1 (003EH)
------------------------------------------------------*/
bit IE_S1R		= ICON1.0;		/* Serial I/O1 Receive Interrupt Enable Bit */
bit IE_S1T		= ICON1.1;		/* Serial I/O1 Transmit Interrupt Enable Bit */
bit IE_S2R		= ICON1.2;		/* Serial I/O2 Receive Interrupt Enable Bit */
bit IE_S2T		= ICON1.3;		/* Serial I/O2 Transmit Interrupt Enable Bit */
bit IE_INT0		= ICON1.4;		/* INT0 Interrupt Enable Bit */
bit IE_INT1		= ICON1.5;		/* INT1 Interrupt Enable Bit */
bit IE_KIU1BC	= ICON1.6;		/* Key-on Wake Up Interrupt Enable Bit */
 								/* UART1 Bus Collision Interrupt Enable Bit */
bit IE_CNTR0	= ICON1.7;		/* CNTR0 Interrupt Enable Bit */

/*------------------------------------------------------
   Interrupt Control Register1 (003FH)
------------------------------------------------------*/
bit IE_CAP0		= ICON2.0;		/* Capture 0 Interrupt Enable Bit */
bit IE_CAP1		= ICON2.1;		/* Capture 1 Interrupt Enable Bit */
bit IE_CMP		= ICON2.2;		/* Compare Interrupt Enable Bit */
bit IE_TX		= ICON2.3;		/* Timer X Interrupt Enable Bit */
bit IE_TA		= ICON2.4;		/* Timer A Interrupt Enable Bit */
bit IE_TB		= ICON2.5;		/* Timer B Interrupt Enable Bit */
bit IE_ADT1		= ICON2.6;		/* A/D Conversion Interrupt Enable Bit */
								/* Timer 1 Interrupt Enable Bit */