2.5 ghz in fr4.txt

来自「high speed pcb stackup」· 文本 代码 · 共 66 行

2.5Ghz in FR4.


It is possible to use common FR4 in 2.5 GHz systems, but you 
need to follow a few design constraints: 


* Do not use stripline. The discontinuities presented by 
the vias are most often killers. Avoid all vias in the high 
speed nets and use microstrip (i.e., top-surface only). 


* Use wide traces. FR4 is lossy at 2.5 GHz, so try to compensate 
for the high dielectric loss by decreasing the metal loss. Use 
wider traces which will reduce the resistive losses in the metal. 


* Use short traces. If you need to route 2.5 GHz signals 
on nets that are 10 inches (25 cm) long, I doubt if your 
system will function. Keep the traces *short* (say, less 
than 1 inch [2.5 cm]). 

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In terms of reference planes, having one set of signals reference 
one plane and another set of signals reference another plane 
should be okay, but I *strongly* recommend that: 

        * the reference plane for a set of signals is the same 
          supply used by the driving device's output! 
        * in particular, make sure the supply is what the signals 
          are being internally referenced to. For example, ECL 
          signals should be referenced to VTT (-2.0V), *not* 
          VEE (-5.2V). Similar, CML should be referenced to VCC 
          (positive rail) not VEE (negative rail). 
        * for signals that evenly reference two supplies (e.g., full 
          swing CMOS), reference one plane and add plenty of 
          decoupling at the driver. 

/////
VCC and GND are equally noisy. And are equally good references. Imagine - 
all your ref planes are VCCs. And just one is GND. What has changed? 
Nothing. 
  
The difference though is: if you use VCC/GND pairs as ref planes for each 
hi-speed routing layer, you will have to put bunch of de-coupling capacitors 
all over the board to provide for return currents along signals' runs i/o 
putting bunch of vias connecting GNDs together. 
  
What is more expensive I do not know. But the inductance of a cap as a 
return path (cap itself and two vias) is higher than inductance of one via. 

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Your comment about making the via act like a transmission line is correct. 
There are 2 ways that I know of to remove the stub caused by a via: 
  
Blind vias - via stub is completely removed, but fabrication cost is 
doubled. 
Counterboring - basically this method drills out the rest of the via, and it 
adds about 25% to fabrication 
  
Both methods obviously hurt the testability access to the board. The other 
thing you can do is remove all non-functional pads within the via to reduce 
the overall capacitance of the via.