eth_wishbonedma.v

该文件包含以太网IP核的相关代码

// WB_CLK_I is divided by 2. This signal is used for enabling tx and rx operations sequentially
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    Div2 <=#Tp 1'h0;
  else
    Div2 <=#Tp ~Div2;
end


// Tx_En and Rx_En select who can access the BD memory (Tx or Rx)
assign TxEn =  Div2 & r_TxEn;
assign RxEn = ~Div2 & r_RxEn;


// Changes for tx occur every second clock. Flop is used for this manner.
always @ (posedge MTxClk or posedge WB_RST_I)
begin
  if(WB_RST_I)
    Flop <=#Tp 1'b0;
  else
  if(TxDone | TxAbort | TxRetry_q)
    Flop <=#Tp 1'b0;
  else
  if(TxUsedData)
    Flop <=#Tp ~Flop;
end


// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxBDReady <=#Tp 1'b0;
  else
  if(TxEn & TxBDRead)
    TxBDReady <=#Tp BDDataOut[15]; // TxBDReady=BDDataOut[15]   // TxBDReady is sampled only once at the beginning
  else
  if(TxDone & ~TxDone_q | TxAbort & ~TxAbort_q | TxRetry & ~TxRetry_q | ClearTxBDReady | TxPauseRq)
    TxBDReady <=#Tp 1'b0;
end


// Latching READY status of the Tx buffer descriptor
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    begin
      TxPauseRq <=#Tp 1'b0;
    end
  else
  if(TxEn & TxBDRead)
    begin
      TxPauseRq <=#Tp BDDataOut[9];    // Tx PAUSE request
    end
  else
      TxPauseRq <=#Tp 1'b0;
end


assign TxPauseTV[15:0] = TxLength[15:0];

// Reading the Tx buffer descriptor
assign StartTxBDRead = TxEn & ~BlockingTxBDRead & (TxRetry_wb | TxStatusWriteOccured);

always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxBDRead <=#Tp 1'b1;
  else
  if(StartTxBDRead)
    TxBDRead <=#Tp 1'b1;
  else
  if(StartTxDataRead | TxPauseRq)
    TxBDRead <=#Tp 1'b0;
end



// Requesting data (DMA)
assign StartTxDataRead = TxBDRead & TxBDReady & ~TxPauseRq | GetNewTxData_wb;
assign ResetTxDataRead = DMACycleFinishedTx | TxRestartPulse | TxAbortPulse | TxDonePulse;


// Reading data
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxDataRead <=#Tp 1'b0;
  else
  if(StartTxDataRead & r_DmaEn)
    TxDataRead <=#Tp 1'b1;
  else
  if(ResetTxDataRead)
    TxDataRead <=#Tp 1'b0;
end

// Requesting tx data from the DMA
assign WB_REQ_O[0] = TxDataRead;
assign DMACycleFinishedTx = WB_REQ_O[0] & WB_ACK_I[0] & TxBDReady;


// Writing status back to the Tx buffer descriptor
assign StartTxStatusWrite = TxEn & ~BlockingTxStatusWrite & (TxDone_wb | TxAbort_wb | TxCtrlEndFrm_wb);
assign ResetTxStatusWrite = TxStatusWrite;

always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxStatusWrite <=#Tp 1'b0;
  else
  if(StartTxStatusWrite)
    TxStatusWrite <=#Tp 1'b1;
  else
  if(ResetTxStatusWrite)
    TxStatusWrite <=#Tp 1'b0;
end


// Status writing must occur only once. Meanwhile it is blocked.
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    BlockingTxStatusWrite <=#Tp 1'b0;
  else
  if(StartTxStatusWrite)
    BlockingTxStatusWrite <=#Tp 1'b1;
  else
  if(~TxDone_wb & ~TxAbort_wb)
    BlockingTxStatusWrite <=#Tp 1'b0;
end


// After a tx status write is finished, a new tx buffer descriptor is read. Signal must be
// latched because new BD read doesn't occur immediately.
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxStatusWriteOccured <=#Tp 1'b0;
  else
  if(StartTxStatusWrite)
    TxStatusWriteOccured <=#Tp 1'b1;
  else
  if(StartTxBDRead)
    TxStatusWriteOccured <=#Tp 1'b0;
end


// TxBDRead state is activated only once. 
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    BlockingTxBDRead <=#Tp 1'b0;
  else
  if(StartTxBDRead)
    BlockingTxBDRead <=#Tp 1'b1;
  else
  if(TxStartFrm_wb | TxCtrlEndFrm_wb)
    BlockingTxBDRead <=#Tp 1'b0;
end


// Latching status from the tx buffer descriptor
// Data is avaliable one cycle after the access is started (at that time signal TxEn is not active)
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxStatus <=#Tp 32'h0;
  else
  if(TxBDRead & TxEn)
    TxStatus <=#Tp BDDataOut;
end


//Latching length from the buffer descriptor;
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxLength <=#Tp 16'h0;
  else
  if(TxBDRead & TxEn)
    TxLength <=#Tp BDDataOut[31:16];
  else
  if(GetNewTxData_wb & ~WillSendControlFrame)
    begin
      if(TxLength > 4)
        TxLength <=#Tp TxLength - 4;    // Length is subtracted at the data request
      else
        TxLength <=#Tp 16'h0;
    end
end


// Latching Rx buffer descriptor status
// Data is avaliable one cycle after the access is started (at that time signal RxEn is not active)
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    RxStatus <=#Tp 16'h0;
  else
  if(RxBDRead & RxEn)
    RxStatus <=#Tp BDDataOut[15:0];
end


// Signal GetNewTxData_wb that requests new data from the DMA must be latched since the DMA response
// might be delayed.
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    GetNewTxData_wb_latched <=#Tp 1'b0;
  else
  if(GetNewTxData_wb)
    GetNewTxData_wb_latched <=#Tp 1'b1;
  else
  if(DMACycleFinishedTx)
    GetNewTxData_wb_latched <=#Tp 1'b0;
end


// New tx data is avaliable after the DMA access is finished
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    NewTxDataAvaliable_wb <=#Tp 1'b0;
  else
  if(DMACycleFinishedTx & GetNewTxData_wb_latched)
    NewTxDataAvaliable_wb <=#Tp 1'b1;
  else
  if(NewTxDataAvaliable_wb)
    NewTxDataAvaliable_wb <=#Tp 1'b0;
end


// Tx Buffer descriptor is only read at the beginning. This signal is used for generation of the
// TxStartFrm_wb signal.
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxBDAccessed <=#Tp 1'b0;
  else
  if(TxBDRead)
    TxBDAccessed <=#Tp 1'b1;
  else
  if(TxStartFrm_wb)
    TxBDAccessed <=#Tp 1'b0;
end


// TxStartFrm_wb: indicator of the start frame (synchronized to WB_CLK_I)
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxStartFrm_wb <=#Tp 1'b0;
  else
  if(DMACycleFinishedTx & TxBDAccessed & ~TxStartFrm_wb)
    TxStartFrm_wb <=#Tp 1'b1;
  else
  if(TxStartFrm_wb)
    TxStartFrm_wb <=#Tp 1'b0;
end


// TxEndFrm_wb: indicator of the end of frame
assign TxEndFrm_wb = (TxLength <= 4) & TxUsedData;


// Input latch of the end-of-frame indicator
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxEndFrm_wbLatched <=#Tp 1'b0;
  else
  if(TxEndFrm_wb)
    TxEndFrm_wbLatched <=#Tp 1'b1;
  else
  if(TxRestartPulse | TxDonePulse | TxAbortPulse)
    TxEndFrm_wbLatched <=#Tp 1'b0;
end


// Marks which bytes are valid within the word.
assign TxValidBytes = (TxLength >= 4)? 2'b0 : TxLength[1:0];


// Latching valid bytes
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxValidBytesLatched <=#Tp 2'h0;
  else
  if(TxEndFrm_wb & ~TxEndFrm_wbLatched)
    TxValidBytesLatched <=#Tp TxValidBytes;
  else
  if(TxRestartPulse | TxDonePulse | TxAbortPulse)
    TxValidBytesLatched <=#Tp 2'h0;
end


// Input Tx data latch 
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxDataLatched_wb <=#Tp 32'h0;
  else
  if(DMACycleFinishedTx)
    TxDataLatched_wb <=#Tp WB_DAT_I;
end


// TxStartFrmRequest is set when a new frame is avaliable or when new data of the same frame is avaliable)
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxStartFrmRequest <=#Tp 1'b0;
  else
  if(TxStartFrm_wb | NewTxDataAvaliable_wb)
    TxStartFrmRequest <=#Tp TxStartFrm_wb;
end


// Bit 14 is used as a wrap bit. When active it indicates the last buffer descriptor in a row. After
// using this descriptor, first BD will be used again.



// TX
// bit 15 od tx je ready
// bit 14 od tx je interrupt (Tx buffer ali tx error bit se postavi v interrupt registru, ko se ta buffer odda)
// bit 13 od tx je wrap
// bit 12 od tx je pad
// bit 11 od tx je crc
// bit 10 od tx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9  od tx je pause request (control frame)
    // Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8  od tx je defer indication
// bit 7  od tx je late collision
// bit 6  od tx je retransmittion limit
// bit 5  od tx je underrun
// bit 4  od tx je carrier sense lost
// bit [3:0] od tx je retry count

//assign TxBDReady      = TxStatus[15];     // already used
assign TxIRQEn          = TxStatus[14];
assign WrapTxStatusBit  = TxStatus[13];                                                   // ok povezan
assign PerPacketPad     = TxStatus[12];                                                   // ok povezan
assign PerPacketCrcEn   = TxStatus[11] & TxStatus[10];      // When last is also set      // ok povezan
//assign TxPauseRq      = TxStatus[9];      // already used



// RX
// bit 15 od rx je empty
// bit 14 od rx je interrupt (Rx buffer ali rx frame received se postavi v interrupt registru, ko se ta buffer zapre)
// bit 13 od rx je wrap
// bit 12 od rx je reserved
// bit 11 od rx je reserved
// bit 10 od rx je last (crc se doda le ce je bit 11 in hkrati bit 10)
// bit 9  od rx je pause request (control frame)
    // Vsi zgornji biti gredo ven, spodnji biti (od 8 do 0) pa so statusni in se vpisejo po koncu oddajanja
// bit 8  od rx je defer indication
// bit 7  od rx je late collision
// bit 6  od rx je retransmittion limit
// bit 5  od rx je underrun
// bit 4  od rx je carrier sense lost
// bit [3:0] od rx je retry count

assign WrapRxStatusBit = RxStatus[13];


// Temporary Tx and Rx buffer descriptor address 
assign TempTxBDAddress[7:0] = {8{ TxStatusWrite    & ~WrapTxStatusBit}} & (TxBDAddress + 1) ; // Tx BD increment or wrap (last BD)
assign TempRxBDAddress[7:0] = {8{ WrapRxStatusBit}} & (r_TxBDNum)       | // Using first Rx BD
                              {8{~WrapRxStatusBit}} & (RxBDAddress + 1) ; // Using next Rx BD (incremenrement address)


// Latching Tx buffer descriptor address
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    TxBDAddress <=#Tp 8'h0;
  else
  if(TxStatusWrite)
    TxBDAddress <=#Tp TempTxBDAddress;
end


// Latching Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    RxBDAddress <=#Tp 8'h0;
  else
  if(TX_BD_NUM_Wr)                        // When r_TxBDNum is updated, RxBDAddress is also
    RxBDAddress <=#Tp WB_DAT_I[7:0];
  else
  if(RxStatusWrite)
    RxBDAddress <=#Tp TempRxBDAddress;
end


// Selecting Tx or Rx buffer descriptor address
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    BDAddress <=#Tp 8'h0;
  else
  if(TxEn)
    BDAddress <=#Tp TxBDAddress;
  else
    BDAddress <=#Tp RxBDAddress;
end


assign RxLength[15:0]  = 16'h1399;
assign NewRxStatus[15:0] = {1'b0, WbWriteError, RxStatus[13:0]};