eth_wishbonedma.v

该文件包含以太网IP核的相关代码

//////////////////////////////////////////////////////////////////////
////                                                              ////
////  eth_wishbonedma.v                                           ////
////                                                              ////
////  This file is part of the Ethernet IP core project           ////
////  http://www.opencores.org/cores/ethmac/                      ////
////                                                              ////
////  Author(s):                                                  ////
////      - Igor Mohor ([e-mail])                      ////
////                                                              ////
////  All additional information is avaliable in the Readme.txt   ////
////  file.                                                       ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2001 Authors                                   ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_wishbonedma.v,v $
// Revision 1.9  2001/12/05 15:00:16  mohor
// RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
// instead of the number of RX descriptors).
//
// Revision 1.8  2001/12/05 10:45:59  mohor
// ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.
//
// Revision 1.7  2001/11/13 14:23:56  mohor
// Generic memory model is used. Defines are changed for the same reason.
//
// Revision 1.6  2001/10/19 11:24:29  mohor
// Number of addresses (wb_adr_i) minimized.
//
// Revision 1.5  2001/10/19 08:43:51  mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.4  2001/10/18 12:07:11  mohor
// Status signals changed, Adress decoding changed, interrupt controller
// added.
//
// Revision 1.3  2001/09/24 15:02:56  mohor
// Defines changed (All precede with ETH_). Small changes because some
// tools generate warnings when two operands are together. Synchronization
// between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
// demands).
//
// Revision 1.2  2001/08/08 08:28:21  mohor
// "else" was missing within the always block in file eth_wishbonedma.v.
//
// Revision 1.1  2001/08/06 14:44:29  mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1  2001/07/30 21:23:42  mohor
// Directory structure changed. Files checked and joind together.
//
//
//
//
//


`include "eth_defines.v"
`include "timescale.v"


module eth_wishbonedma
   (

    // WISHBONE common
    WB_CLK_I, WB_RST_I, WB_DAT_I, WB_DAT_O, 

    // WISHBONE slave
 		WB_ADR_I, WB_SEL_I, WB_WE_I, WB_ACK_O, 
 		WB_REQ_O, WB_ACK_I, WB_ND_O, WB_RD_O, BDCs, 

    //TX
    MTxClk, TxStartFrm, TxEndFrm, TxUsedData, TxData, StatusIzTxEthMACModula, 
    TxRetry, TxAbort, TxUnderRun, TxDone, TPauseRq, TxPauseTV, PerPacketCrcEn, 
    PerPacketPad, 

    //RX
    MRxClk, RxData, RxValid, RxStartFrm, RxEndFrm, 
    
    // Register
    r_TxEn, r_RxEn, r_TxBDNum, r_DmaEn, TX_BD_NUM_Wr, 

    WillSendControlFrame, TxCtrlEndFrm, 
    
    // Interrupts
    TxB_IRQ, TxE_IRQ, RxB_IRQ, RxF_IRQ, Busy_IRQ

		);


parameter Tp = 1;

// WISHBONE common
input           WB_CLK_I;       // WISHBONE clock
input           WB_RST_I;       // WISHBONE reset
input  [31:0]   WB_DAT_I;       // WISHBONE data input
output [31:0]   WB_DAT_O;       // WISHBONE data output

// WISHBONE slave
input   [9:2]   WB_ADR_I;       // WISHBONE address input
input   [3:0]   WB_SEL_I;       // WISHBONE byte select input
input           WB_WE_I;        // WISHBONE write enable input
input           BDCs;           // Buffer descriptors are selected
output          WB_ACK_O;       // WISHBONE acknowledge output

// DMA
input   [1:0]   WB_ACK_I;       // DMA acknowledge input
output  [1:0]   WB_REQ_O;       // DMA request output
output  [1:0]   WB_ND_O;        // DMA force new descriptor output
output          WB_RD_O;        // DMA restart descriptor output

// Tx
input           MTxClk;         // Transmit clock (from PHY)
input           TxUsedData;     // Transmit packet used data
input  [15:0]   StatusIzTxEthMACModula;
input           TxRetry;        // Transmit packet retry
input           TxAbort;        // Transmit packet abort
input           TxDone;         // Transmission ended
output          TxStartFrm;     // Transmit packet start frame
output          TxEndFrm;       // Transmit packet end frame
output  [7:0]   TxData;         // Transmit packet data byte
output          TxUnderRun;     // Transmit packet under-run
output          PerPacketCrcEn; // Per packet crc enable
output          PerPacketPad;   // Per packet pading
output          TPauseRq;       // Tx PAUSE control frame
output [15:0]   TxPauseTV;      // PAUSE timer value
input           WillSendControlFrame;
input           TxCtrlEndFrm;

// Rx
input           MRxClk;         // Receive clock (from PHY)
input   [7:0]   RxData;         // Received data byte (from PHY)
input           RxValid;        // 
input           RxStartFrm;     // 
input           RxEndFrm;       // 

//Register
input           r_TxEn;         // Transmit enable
input           r_RxEn;         // Receive enable
input   [7:0]   r_TxBDNum;      // Receive buffer descriptor number
input           r_DmaEn;        // DMA enable
input           TX_BD_NUM_Wr;   // RxBDNumber written

// Interrupts
output TxB_IRQ;
output TxE_IRQ;
output RxB_IRQ;
output RxF_IRQ;
output Busy_IRQ;

reg             WB_REQ_O_RX;    
reg             WB_ND_O_TX;     // New descriptor
reg             WB_RD_O;        // Restart descriptor

reg             TxStartFrm;
reg             TxEndFrm;
reg     [7:0]   TxData;

reg             TxUnderRun;
reg             TPauseRq;
reg             TxPauseRq;

reg             RxStartFrm_wb;
reg     [31:0]  RxData_wb;
reg             RxDataValid_wb;
reg             RxEndFrm_wb;

reg     [7:0]   BDAddress;    // BD address for access from MAC side
reg             BDRead_q;

reg             TxBDRead;
reg             TxDataRead;
reg             TxStatusWrite;

reg     [1:0]   TxValidBytesLatched;
reg             TxEndFrm_wbLatched;

reg    [15:0]   TxLength;
reg    [31:0]   TxStatus;

reg    [15:0]   RxStatus;

reg             TxStartFrm_wb;
reg             TxRetry_wb;
reg             GetNewTxData_wb;
reg             TxDone_wb;
reg             TxAbort_wb;


reg             TxStartFrmRequest;
reg    [31:0]   TxDataLatched_wb;

reg             RxStatusWriteOccured;

reg             TxRestart_wb_q;
reg             TxDone_wb_q;
reg             TxAbort_wb_q;
reg             RxBDReady;
reg             TxBDReady;

reg             RxBDRead;
reg             RxStatusWrite;
reg             WbWriteError;

reg    [31:0]   TxDataLatched;
reg     [1:0]   TxByteCnt;
reg             LastWord;
reg             GetNewTxData;
reg             TxRetryLatched;

reg             Div2;
reg             Flop;

reg             BlockingTxStatusWrite;
reg             TxStatusWriteOccured;
reg             BlockingTxBDRead;

reg             GetNewTxData_wb_latched;

reg             NewTxDataAvaliable_wb;

reg             TxBDAccessed;

reg     [7:0]   TxBDAddress;
reg     [7:0]   RxBDAddress;

reg             GotDataSync1;
reg             GotDataSync2;
wire            TPauseRqSync2;
wire             GotDataSync3;
reg             GotData;
reg             SyncGetNewTxData_wb1;
reg             SyncGetNewTxData_wb2;
reg             SyncGetNewTxData_wb3;
reg             TxDoneSync1;
reg             TxDoneSync2;
wire             TxDoneSync3;
reg             TxRetrySync1;
reg             TxRetrySync2;
wire            TxRetrySync3;
reg             TxAbortSync1;
reg             TxAbortSync2;
wire            TxAbortSync3;

reg             TxAbort_q;
reg             TxDone_q;
reg             TxRetry_q;
reg             TxUsedData_q;

reg    [31:0]   RxDataLatched2;
reg    [15:0]   RxDataLatched1;
reg     [1:0]   RxValidBytes;
reg     [1:0]   RxByteCnt;
reg             LastByteIn;
reg             ShiftWillEnd;

reg             StartShifting;
reg             Shifting_wb_Sync1;
reg             Shifting_wb_Sync2;
reg             LatchNow_wb;

reg             ShiftEndedSync1;
reg             ShiftEndedSync2;
reg             ShiftEndedSync3;
wire            ShiftEnded;

reg             RxStartFrmSync1;
reg             RxStartFrmSync2;
wire            RxStartFrmSync3;

reg             DMACycleFinishedTx_q;
reg             DataNotAvaliable;

reg             ClearTxBDReadySync1;
reg             ClearTxBDReadySync2;
reg             ClearTxBDReady;

reg             TxCtrlEndFrm_wbSync1;
reg             TxCtrlEndFrm_wbSync2;
wire            TxCtrlEndFrm_wbSync3;
reg             TxCtrlEndFrm_wb;

wire    [15:0]  TxPauseTV;
wire            ResetDataNotAvaliable;
wire            SetDataNotAvaliable;
wire            DWord;                      // Only 32-bit accesses are valid
wire            BDWe;                       // BD Write Enable for access from WISHBONE side
wire            BDRead;                     // BD Read access from WISHBONE side
wire   [31:0]   BDDataIn;                   // BD data in
wire   [31:0]   BDDataOut;                  // BD data out

wire            TxEndFrm_wb;

wire            DMACycleFinishedTx;
wire            BDStatusWrite;

wire            TxEn;
wire            RxEn;
wire            TxRestartPulse;
wire            TxDonePulse;
wire            TxAbortPulse;

wire            StartRxBDRead;
wire            ResetRxBDRead;
wire            StartRxStatusWrite;

wire            ResetShifting_wb;
wire            StartShifting_wb;
wire            DMACycleFinishedRx;

wire   [31:0]   WB_BDDataOut;

wire            StartTxBDRead;
wire            StartTxDataRead;
wire            ResetTxDataRead;
wire            StartTxStatusWrite;
wire            ResetTxStatusWrite;

wire            TxIRQEn;
wire            WrapTxStatusBit;

wire            WrapRxStatusBit;

wire    [1:0]   TxValidBytes;

wire    [7:0]   TempTxBDAddress;
wire    [7:0]   TempRxBDAddress;

wire   [15:0]   RxLength;
wire   [15:0]   NewRxStatus;

wire            SetGotData;
wire            ResetGotData;
wire            GotDataEvaluate;
wire            ResetSyncGetNewTxData_wb;
wire            ResetTxDoneSync;
wire            ResetTxRetrySync;
wire            ResetTxAbortSync;
wire            SetSyncGetNewTxData_wb;

wire            SetTxAbortSync;
wire            ResetShiftEnded;
wire            ResetRxStartFrmSync1;
wire            StartShiftEnded;
wire            StartRxStartFrmSync1;

wire            SetClearTxBDReady;
wire            ResetClearTxBDReady;

wire            ResetTxCtrlEndFrm_wb;
wire            SetTxCtrlEndFrm_wb;
     
     
     
      
assign BDWe   = BDCs &  WB_WE_I;
assign BDRead = BDCs & ~WB_WE_I;
assign WB_ACK_O = BDWe | BDRead & BDRead_q;  // ACK is delayed one clock because of BLOCKRAM properties when performing read



reg EnableRAM;
always @ (posedge WB_CLK_I or posedge WB_RST_I)
begin
  if(WB_RST_I)
    EnableRAM   <=#Tp 1'b0;
  else
  if(BDWe)
    EnableRAM   <=#Tp 1'b1;
  else
    EnableRAM   <=#Tp EnableRAM;
end


// Generic synchronous two-port RAM interface
generic_tpram     #(8, 32)  i_generic_tpram 
(
  .clk_a(WB_CLK_I),   .rst_a(WB_RST_I),         .ce_a(1'b1),        .we_a(BDWe), 
  .oe_a(EnableRAM),   .addr_a(WB_ADR_I[9:2]),   .di_a(WB_DAT_I),    .do_a(WB_BDDataOut),
  
  .clk_b(WB_CLK_I),   .rst_b(WB_RST_I),         .ce_b(EnableRAM),   .we_b(BDStatusWrite), 
  .oe_b(EnableRAM),   .addr_b(BDAddress[7:0]),  .di_b(BDDataIn),    .do_b(BDDataOut)
);