📄 eth_registers.v
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wire [31:0] MAC_ADDR1Out;
wire [31:0] TX_BD_NUMOut;
eth_register #(32) MODER (.DataIn(DataIn), .DataOut(MODEROut), .Write(MODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MODER_DEF));
eth_register #(32) INT_MASK (.DataIn(DataIn), .DataOut(INT_MASKOut), .Write(INT_MASK_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_INT_MASK_DEF));
eth_register #(32) IPGT (.DataIn(DataIn), .DataOut(IPGTOut), .Write(IPGT_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGT_DEF));
eth_register #(32) IPGR1 (.DataIn(DataIn), .DataOut(IPGR1Out), .Write(IPGR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR1_DEF));
eth_register #(32) IPGR2 (.DataIn(DataIn), .DataOut(IPGR2Out), .Write(IPGR2_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_IPGR2_DEF));
eth_register #(32) PACKETLEN (.DataIn(DataIn), .DataOut(PACKETLENOut), .Write(PACKETLEN_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_PACKETLEN_DEF));
eth_register #(32) COLLCONF (.DataIn(DataIn), .DataOut(COLLCONFOut), .Write(COLLCONF_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_COLLCONF_DEF));
// CTRLMODER registers
wire [31:0] DefaultCtrlModer = `ETH_CTRLMODER_DEF;
assign CTRLMODEROut[31:3] = 29'h0;
eth_register #(3) CTRLMODER2 (.DataIn(DataIn[2:0]), .DataOut(CTRLMODEROut[2:0]), .Write(CTRLMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(DefaultCtrlModer[2:0]));
// End: CTRLMODER registers
eth_register #(32) MIIMODER (.DataIn(DataIn), .DataOut(MIIMODEROut), .Write(MIIMODER_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIMODER_DEF));
assign MIICOMMANDOut[31:3] = 29'h0;
eth_register #(1) MIICOMMAND2 (.DataIn(DataIn[2]), .DataOut(MIICOMMANDOut[2]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | WCtrlDataStart), .Default(1'b0));
eth_register #(1) MIICOMMAND1 (.DataIn(DataIn[1]), .DataOut(MIICOMMANDOut[1]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset | RStatStart), .Default(1'b0));
eth_register #(1) MIICOMMAND0 (.DataIn(DataIn[0]), .DataOut(MIICOMMANDOut[0]), .Write(MIICOMMAND_Wr), .Clk(Clk), .Reset(Reset), .Default(1'b0));
eth_register #(32) MIIADDRESS (.DataIn(DataIn), .DataOut(MIIADDRESSOut), .Write(MIIADDRESS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIADDRESS_DEF));
eth_register #(32) MIITX_DATA (.DataIn(DataIn), .DataOut(MIITX_DATAOut), .Write(MIITX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIITX_DATA_DEF));
eth_register #(32) MIIRX_DATA (.DataIn({16'h0, Prsd}), .DataOut(MIIRX_DATAOut), .Write(MIIRX_DATA_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIIRX_DATA_DEF));
//eth_register #(32) MIISTATUS (.DataIn(DataIn), .DataOut(MIISTATUSOut), .Write(MIISTATUS_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MIISTATUS_DEF));
eth_register #(32) MAC_ADDR0 (.DataIn(DataIn), .DataOut(MAC_ADDR0Out), .Write(MAC_ADDR0_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR0_DEF));
eth_register #(32) MAC_ADDR1 (.DataIn(DataIn), .DataOut(MAC_ADDR1Out), .Write(MAC_ADDR1_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_MAC_ADDR1_DEF));
assign TX_BD_NUMOut[31:8] = 24'h0;
eth_register #(8) TX_BD_NUM (.DataIn(DataIn[7:0]), .DataOut(TX_BD_NUMOut[7:0]), .Write(TX_BD_NUM_Wr), .Clk(Clk), .Reset(Reset), .Default(`ETH_TX_BD_NUM_DEF));
reg LinkFailRegister;
wire ResetLinkFailRegister = Address == `ETH_MIISTATUS_ADR & Read;
reg ResetLinkFailRegister_q1;
reg ResetLinkFailRegister_q2;
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
begin
LinkFailRegister <= #Tp 0;
ResetLinkFailRegister_q1 <= #Tp 0;
ResetLinkFailRegister_q2 <= #Tp 0;
end
else
begin
ResetLinkFailRegister_q1 <= #Tp ResetLinkFailRegister;
ResetLinkFailRegister_q2 <= #Tp ResetLinkFailRegister_q1;
if(LinkFail)
LinkFailRegister <= #Tp 1;
if(~ResetLinkFailRegister_q1 & ResetLinkFailRegister_q2)
LinkFailRegister <= #Tp 0;
end
end
always @ (Address or Read or MODEROut or INT_SOURCEOut or INT_MASKOut or IPGTOut or
IPGR1Out or IPGR2Out or PACKETLENOut or COLLCONFOut or CTRLMODEROut or
MIIMODEROut or MIICOMMANDOut or MIIADDRESSOut or MIITX_DATAOut or
MIIRX_DATAOut or MIISTATUSOut or MAC_ADDR0Out or MAC_ADDR1Out or
TX_BD_NUMOut)
begin
if(Read) // read
begin
case(Address)
`ETH_MODER_ADR : DataOut<=MODEROut;
`ETH_INT_SOURCE_ADR : DataOut<=INT_SOURCEOut;
`ETH_INT_MASK_ADR : DataOut<=INT_MASKOut;
`ETH_IPGT_ADR : DataOut<=IPGTOut;
`ETH_IPGR1_ADR : DataOut<=IPGR1Out;
`ETH_IPGR2_ADR : DataOut<=IPGR2Out;
`ETH_PACKETLEN_ADR : DataOut<=PACKETLENOut;
`ETH_COLLCONF_ADR : DataOut<=COLLCONFOut;
`ETH_CTRLMODER_ADR : DataOut<=CTRLMODEROut;
`ETH_MIIMODER_ADR : DataOut<=MIIMODEROut;
`ETH_MIICOMMAND_ADR : DataOut<=MIICOMMANDOut;
`ETH_MIIADDRESS_ADR : DataOut<=MIIADDRESSOut;
`ETH_MIITX_DATA_ADR : DataOut<=MIITX_DATAOut;
`ETH_MIIRX_DATA_ADR : DataOut<=MIIRX_DATAOut;
`ETH_MIISTATUS_ADR : DataOut<=MIISTATUSOut;
`ETH_MAC_ADDR0_ADR : DataOut<=MAC_ADDR0Out;
`ETH_MAC_ADDR1_ADR : DataOut<=MAC_ADDR1Out;
`ETH_TX_BD_NUM_ADR : DataOut<=TX_BD_NUMOut;
default: DataOut<=32'h0;
endcase
end
else
DataOut<=32'h0;
end
assign r_DmaEn = MODEROut[17];
assign r_RecSmall = MODEROut[16];
assign r_Pad = MODEROut[15];
assign r_HugEn = MODEROut[14];
assign r_CrcEn = MODEROut[13];
assign r_DlyCrcEn = MODEROut[12];
assign r_Rst = MODEROut[11];
assign r_FullD = MODEROut[10];
assign r_ExDfrEn = MODEROut[9];
assign r_NoBckof = MODEROut[8];
assign r_LoopBck = MODEROut[7];
assign r_IFG = MODEROut[6];
assign r_Pro = MODEROut[5];
assign r_Iam = MODEROut[4];
assign r_Bro = MODEROut[3];
assign r_NoPre = MODEROut[2];
assign r_TxEn = MODEROut[1];
assign r_RxEn = MODEROut[0];
assign r_IPGT[6:0] = IPGTOut[6:0];
assign r_IPGR1[6:0] = IPGR1Out[6:0];
assign r_IPGR2[6:0] = IPGR2Out[6:0];
assign r_MinFL[15:0] = PACKETLENOut[31:16];
assign r_MaxFL[15:0] = PACKETLENOut[15:0];
assign r_MaxRet[3:0] = COLLCONFOut[19:16];
assign r_CollValid[5:0] = COLLCONFOut[5:0];
assign r_TxFlow = CTRLMODEROut[2];
assign r_RxFlow = CTRLMODEROut[1];
assign r_PassAll = CTRLMODEROut[0];
assign r_MiiMRst = MIIMODEROut[10];
assign r_MiiNoPre = MIIMODEROut[8];
assign r_ClkDiv[7:0] = MIIMODEROut[7:0];
assign r_WCtrlData = MIICOMMANDOut[2];
assign r_RStat = MIICOMMANDOut[1];
assign r_ScanStat = MIICOMMANDOut[0];
assign r_RGAD[4:0] = MIIADDRESSOut[12:8];
assign r_FIAD[4:0] = MIIADDRESSOut[4:0];
assign r_CtrlData[15:0] = MIITX_DATAOut[15:0];
assign MIISTATUSOut[31:10] = 22'h0 ;
assign MIISTATUSOut[9] = NValid_stat ;
assign MIISTATUSOut[8] = Busy_stat ;
assign MIISTATUSOut[7:3]= 5'h0 ;
assign MIISTATUSOut[2] = 1'b0;
assign MIISTATUSOut[1] = 1'b0;
assign MIISTATUSOut[0] = LinkFailRegister ;
assign r_MAC[31:0] = MAC_ADDR0Out[31:0];
assign r_MAC[47:32] = MAC_ADDR1Out[15:0];
assign r_TxBDNum[7:0] = TX_BD_NUMOut[7:0];
// Interrupt generation
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txb <= 1'b0;
else
if(TxB_IRQ & INT_MASKOut[0])
irq_txb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[0])
irq_txb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_txe <= 1'b0;
else
if(TxE_IRQ & INT_MASKOut[1])
irq_txe <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[1])
irq_txe <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxb <= 1'b0;
else
if(RxB_IRQ & INT_MASKOut[2])
irq_rxb <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[2])
irq_rxb <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_rxf <= 1'b0;
else
if(RxF_IRQ & INT_MASKOut[3])
irq_rxf <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[3])
irq_rxf <= #Tp 1'b0;
end
always @ (posedge Clk or posedge Reset)
begin
if(Reset)
irq_busy <= 1'b0;
else
if(Busy_IRQ & INT_MASKOut[4])
irq_busy <= #Tp 1'b1;
else
if(INT_SOURCE_Wr & DataIn[4])
irq_busy <= #Tp 1'b0;
end
// Generating interrupt signal
assign int_o = irq_txb | irq_txe | irq_rxb | irq_rxf | irq_busy;
// For reading interrupt status
assign INT_SOURCEOut = {28'h0, irq_busy, irq_rxf, irq_rxb, irq_txe, irq_txb};
endmodule
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