_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity InsReg is
    port(
        Q               : out    vl_logic_vector(31 downto 0);
        INSTR           : in     vl_logic_vector(31 downto 0);
        CLK             : in     vl_logic;
        EN              : in     vl_logic;
        NOP             : in     vl_logic;
        RESET           : in     vl_logic
    );
end InsReg;