_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity RegGroup32 is
    port(
        QA              : out    vl_logic_vector(31 downto 0);
        QB              : out    vl_logic_vector(31 downto 0);
        D               : in     vl_logic_vector(31 downto 0);
        clk_up          : in     vl_logic;
        selRA           : in     vl_logic_vector(4 downto 0);
        selRB           : in     vl_logic_vector(4 downto 0);
        selW            : in     vl_logic_vector(4 downto 0);
        enable_1        : in     vl_logic
    );
end RegGroup32;