_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity PreRead is
    port(
        \out\           : out    vl_logic_vector(31 downto 0);
        valid           : out    vl_logic;
        ra              : in     vl_logic_vector(4 downto 0);
        wrAIR           : in     vl_logic_vector(31 downto 0);
        wrAID           : in     vl_logic_vector(22 downto 0);
        wrBIR           : in     vl_logic_vector(31 downto 0);
        wrBID           : in     vl_logic_vector(22 downto 0);
        outWrA          : in     vl_logic_vector(31 downto 0);
        outWrB          : in     vl_logic_vector(31 downto 0)
    );
end PreRead;