_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity Reg32v2 is
    port(
        Q               : out    vl_logic_vector(31 downto 0);
        D1              : in     vl_logic_vector(31 downto 0);
        D2              : in     vl_logic_vector(31 downto 0);
        clk_up          : in     vl_logic;
        enable_1        : in     vl_logic;
        clear_0         : in     vl_logic;
        selW            : in     vl_logic
    );
end Reg32v2;