_primary.vhd

两条5级的并行流水线

library verilog;
use verilog.vl_types.all;
entity SysInsCtrl is
    port(
        SysReg0         : out    vl_logic;
        SysFlagEn       : out    vl_logic;
        IR0B            : out    vl_logic_vector(31 downto 0);
        ID0B            : out    vl_logic_vector(31 downto 0);
        NReadIns        : out    vl_logic;
        PCNext          : in     vl_logic_vector(31 downto 0);
        PC2B            : in     vl_logic_vector(31 downto 0);
        preIR           : in     vl_logic_vector(31 downto 0);
        preID           : in     vl_logic_vector(31 downto 0);
        IR1A            : in     vl_logic_vector(31 downto 0);
        IR1B            : in     vl_logic_vector(31 downto 0);
        IR2A            : in     vl_logic_vector(31 downto 0);
        IR2B            : in     vl_logic_vector(31 downto 0);
        IR3A            : in     vl_logic_vector(31 downto 0);
        IR3B            : in     vl_logic_vector(31 downto 0);
        ID1A            : in     vl_logic_vector(31 downto 0);
        ID1B            : in     vl_logic_vector(31 downto 0);
        ID2A            : in     vl_logic_vector(31 downto 0);
        ID2B            : in     vl_logic_vector(31 downto 0);
        ID3A            : in     vl_logic_vector(31 downto 0);
        ID3B            : in     vl_logic_vector(31 downto 0);
        INTR            : in     vl_logic;
        INTRType        : in     vl_logic_vector(7 downto 0);
        clk             : in     vl_logic;
        reset           : in     vl_logic
    );
end SysInsCtrl;