📄 iolpc2378.h
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/* Transmit Consume Index Register */
typedef struct{
__REG32 TXCONSUMEINDEX :16;
__REG32 :16;
}__txcomind_bits;
/* Transmit Status Vector 0 Register */
typedef struct{
__REG32 CCR_ERR : 1;
__REG32 LCERR : 1;
__REG32 LOOR : 1;
__REG32 DONE : 1;
__REG32 MULTICAST : 1;
__REG32 BROADCAST : 1;
__REG32 PD : 1;
__REG32 ED : 1;
__REG32 EC : 1;
__REG32 LC : 1;
__REG32 GIANT : 1;
__REG32 UNDERRUN : 1;
__REG32 TB :16;
__REG32 CF : 1;
__REG32 PAUSE : 1;
__REG32 BACKPRESSURE : 1;
__REG32 VLAN : 1;
}__tsv0_bits;
/* Transmit Status Vector 1 Register */
typedef struct{
__REG32 TBC :16;
__REG32 TCC : 4;
__REG32 :12;
}__tsv1_bits;
/* Receive Status Vector Register */
typedef struct{
__REG32 RBC :16;
__REG32 PPI : 1;
__REG32 RXDVEPS : 1;
__REG32 CEPS : 1;
__REG32 RCV : 1;
__REG32 CRC_ERR : 1;
__REG32 LCE : 1;
__REG32 LOOR : 1;
__REG32 R_OK : 1;
__REG32 MULTICAST : 1;
__REG32 BROADCAST : 1;
__REG32 DN : 1;
__REG32 CF : 1;
__REG32 PAUSE : 1;
__REG32 UO : 1;
__REG32 VLAN : 1;
__REG32 : 1;
}__rsv_bits;
/* Flow Control Counter Register */
typedef struct{
__REG32 MC :16;
__REG32 PT :16;
}__fwctrlcnt_bits;
/* Flow Control Status Register */
typedef struct{
__REG32 MCC :16;
__REG32 :16;
}__fwctrlstat_bits;
/* Receive Filter Control Register */
typedef struct{
__REG32 AUE : 1;
__REG32 ABE : 1;
__REG32 AME : 1;
__REG32 AUHE : 1;
__REG32 AMHE : 1;
__REG32 APE : 1;
__REG32 : 6;
__REG32 MPEWOL : 1;
__REG32 RXFEWOL : 1;
__REG32 :18;
}__rxflctrl_bits;
/* Receive Filter WoL Status Register */
typedef struct{
__REG32 AUWOL : 1;
__REG32 ABWOL : 1;
__REG32 AMWOL : 1;
__REG32 AUHWOL : 1;
__REG32 AMHWOL : 1;
__REG32 APWOL : 1;
__REG32 : 1;
__REG32 RXFWOL : 1;
__REG32 MPWOL : 1;
__REG32 :23;
}__rxflwolstat_bits;
/* Receive Filter WoL Clear Register */
typedef struct{
__REG32 AUWOLC : 1;
__REG32 ABWOLC : 1;
__REG32 AMWOLC : 1;
__REG32 AUHWOLC : 1;
__REG32 AMHWOLC : 1;
__REG32 APWOLC : 1;
__REG32 : 1;
__REG32 RXFWOLC : 1;
__REG32 MPWOLC : 1;
__REG32 :23;
}__rxflwolclr_bits;
/* Interrupt Status Register */
typedef struct{
__REG32 RXOVERRUNINT : 1;
__REG32 RXERRORINT : 1;
__REG32 RXFINISHEDINT : 1;
__REG32 RXDONEINT : 1;
__REG32 TXUNDERRUNINT : 1;
__REG32 TXERRORINT : 1;
__REG32 TXFINISHEDINT : 1;
__REG32 TXDONEINT : 1;
__REG32 : 4;
__REG32 SOFTINT : 1;
__REG32 WAKEUPINT : 1;
__REG32 :18;
}__intstat_bits;
/* Interrupt Enable Register */
typedef struct{
__REG32 RXOVERRUNINTEN : 1;
__REG32 RXERRORINTEN : 1;
__REG32 RXFINISHEDINTEN : 1;
__REG32 RXDONEINTEN : 1;
__REG32 TXUNDERRUNINTEN : 1;
__REG32 TXERRORINTEN : 1;
__REG32 TXFINISHEDINTEN : 1;
__REG32 TXDONEINTEN : 1;
__REG32 : 4;
__REG32 SOFTINTEN : 1;
__REG32 WAKEUPINTEN : 1;
__REG32 :18;
}__intena_bits;
/* Interrupt Clear Register */
typedef struct{
__REG32 RXOVERRUNINTCLR : 1;
__REG32 RXERRORINTCLR : 1;
__REG32 RXFINISHEDINTCLR: 1;
__REG32 RXDONEINTCLR : 1;
__REG32 TXUNDERRUNINTCLR: 1;
__REG32 TXERRORINTCLR : 1;
__REG32 TXFINISHEDINTCLR: 1;
__REG32 TXDONEINTCLR : 1;
__REG32 : 4;
__REG32 SOFTINTCLR : 1;
__REG32 WAKEUPINTCLR : 1;
__REG32 :18;
}__intclr_bits;
/* Interrupt Set Register */
typedef struct{
__REG32 RXOVERRUNINTSET : 1;
__REG32 RXERRORINTSET : 1;
__REG32 RXFINISHEDINTSET: 1;
__REG32 RXDONEINTSET : 1;
__REG32 TXUNDERRUNINTSET: 1;
__REG32 TXERRORINTSET : 1;
__REG32 TXFINISHEDINTSET: 1;
__REG32 TXDONEINTSET : 1;
__REG32 : 4;
__REG32 SOFTINTSET : 1;
__REG32 WAKEUPINTSET : 1;
__REG32 :18;
}__intset_bits;
/* Power Down Register */
typedef struct{
__REG32 :31;
__REG32 POWERDOWN : 1;
}__pwrdn_bits;
/* USB - Device Interrupt Status Register */
typedef struct {
__REG32 PORTSEL : 2;
__REG32 :30;
} __usbportsel_bits;
/* USB Clock Control register (USBClkCtrl - 0xFFE0 CFF4)
USB Clock Status register (USBClkSt - 0xFFE0 CFF8) */
typedef struct{
__REG32 : 1;
__REG32 DEV_CLK_EN : 1;
__REG32 : 1;
__REG32 PORTSEL_CLK_EN : 1;
__REG32 AHB_CLK_EN : 1;
__REG32 :27;
} __usbclkctrl_bits;
/* USB - Device Interrupt Status Register */
typedef struct {
__REG32 USB_INT_REQ_LP : 1;
__REG32 USB_INT_REQ_HP : 1;
__REG32 USB_INT_REQ_DMA : 1;
__REG32 : 5;
__REG32 USB_NEED_CLOCK : 1;
__REG32 :22;
__REG32 EN_USB_INTS : 1;
} __usbints_bits;
/* USB - Device Interrupt Status Register */
/* USB - Device Interrupt Enable Register */
/* USB - Device Interrupt Clear Register */
/* USB - Device Interrupt Set Register */
typedef struct {
__REG32 FRAME : 1;
__REG32 EP_FAST : 1;
__REG32 EP_SLOW : 1;
__REG32 DEV_STAT : 1;
__REG32 CCEMTY : 1;
__REG32 CDFULL : 1;
__REG32 RXENDPKT : 1;
__REG32 TXENDPKT : 1;
__REG32 EP_RLZED : 1;
__REG32 ERR_INT : 1;
__REG32 :22;
} __usbdevintst_bits;
/* USB - Device Interrupt Priority Register */
typedef struct {
__REG8 FRAME : 1;
__REG8 EP_FAST : 1;
__REG8 : 6;
} __usbdevintpri_bits;
/* USB - Endpoint Interrupt Status Register */
/* USB - Endpoint Interrupt Enable Register */
/* USB - Endpoint Interrupt Clear Register */
/* USB - Endpoint Interrupt Set Register */
/* USB - Endpoint Interrupt Priority Register */
typedef struct {
__REG32 EP_0RX : 1;
__REG32 EP_0TX : 1;
__REG32 EP_1RX : 1;
__REG32 EP_1TX : 1;
__REG32 EP_2RX : 1;
__REG32 EP_2TX : 1;
__REG32 EP_3RX : 1;
__REG32 EP_3TX : 1;
__REG32 EP_4RX : 1;
__REG32 EP_4TX : 1;
__REG32 EP_5RX : 1;
__REG32 EP_5TX : 1;
__REG32 EP_6RX : 1;
__REG32 EP_6TX : 1;
__REG32 EP_7RX : 1;
__REG32 EP_7TX : 1;
__REG32 EP_8RX : 1;
__REG32 EP_8TX : 1;
__REG32 EP_9RX : 1;
__REG32 EP_9TX : 1;
__REG32 EP_10RX : 1;
__REG32 EP_10TX : 1;
__REG32 EP_11RX : 1;
__REG32 EP_11TX : 1;
__REG32 EP_12RX : 1;
__REG32 EP_12TX : 1;
__REG32 EP_13RX : 1;
__REG32 EP_13TX : 1;
__REG32 EP_14RX : 1;
__REG32 EP_14TX : 1;
__REG32 EP_15RX : 1;
__REG32 EP_15TX : 1;
} __usbepintst_bits;
/* USB - Realize Enpoint Register */
/* USB - DMA Request Status Register */
/* USB - DMA Request Clear Register */
/* USB - DMA Request Set Regiser */
/* USB - EP DMA Status Register */
/* USB - EP DMA Enable Register */
/* USB - EP DMA Disable Register */
/* USB - New DD Request Interrupt Status Register */
/* USB - New DD Request Interrupt Clear Register */
/* USB - New DD Request Interrupt Set Register */
/* USB - End Of Transfer Interrupt Status Register */
/* USB - End Of Transfer Interrupt Clear Register */
/* USB - End Of Transfer Interrupt Set Register */
/* USB - System Error Interrupt Status Register */
/* USB - System Error Interrupt Clear Register */
/* USB - System Error Interrupt Set Register */
typedef struct {
__REG32 EP0 : 1;
__REG32 EP1 : 1;
__REG32 EP2 : 1;
__REG32 EP3 : 1;
__REG32 EP4 : 1;
__REG32 EP5 : 1;
__REG32 EP6 : 1;
__REG32 EP7 : 1;
__REG32 EP8 : 1;
__REG32 EP9 : 1;
__REG32 EP10 : 1;
__REG32 EP11 : 1;
__REG32 EP12 : 1;
__REG32 EP13 : 1;
__REG32 EP14 : 1;
__REG32 EP15 : 1;
__REG32 EP16 : 1;
__REG32 EP17 : 1;
__REG32 EP18 : 1;
__REG32 EP19 : 1;
__REG32 EP20 : 1;
__REG32 EP21 : 1;
__REG32 EP22 : 1;
__REG32 EP23 : 1;
__REG32 EP24 : 1;
__REG32 EP25 : 1;
__REG32 EP26 : 1;
__REG32 EP27 : 1;
__REG32 EP28 : 1;
__REG32 EP29 : 1;
__REG32 EP30 : 1;
__REG32 EP31 : 1;
} __usbreep_bits;
/* USB - Endpoint Index Register */
typedef struct {
__REG32 PHY_ENDP : 5;
__REG32 :27;
} __usbepin_bits;
/* USB - MaxPacketSize Register */
typedef struct {
__REG32 MPS :10;
__REG32 :22;
} __usbmaxpsize_bits;
/* USB - Receive Packet Length Register */
typedef struct {
__REG32 PKT_LNGTH :10;
__REG32 DV : 1;
__REG32 PKT_RDY : 1;
__REG32 :20;
} __usbrxplen_bits;
/* USB - Transmit Packet Length Register */
typedef struct {
__REG32 PKT_LNGHT :10;
__REG32 :22;
} __usbtxplen_bits;
/* USB - Control Register */
typedef struct {
__REG32 RD_EN : 1;
__REG32 WR_EN : 1;
__REG32 LOG_ENDPOINT : 4;
__REG32 :26;
} __usbctrl_bits;
/* USB - Command Code Register */
typedef struct {
__REG32 : 8;
__REG32 CMD_PHASE : 8;
__REG32 CMD_CODE : 8;
__REG32 : 8;
} __usbcmdcode_bits;
/* USB - Command Data Register */
typedef struct {
__REG32 CMD_DATA : 8;
__REG32 :24;
} __usbcmddata_bits;
/* USB - DMA Interrupt Status Register */
/* USB - DMA Interrupt Enable Register */
typedef struct {
__REG32 EOT : 1;
__REG32 NDDR : 1;
__REG32 ERR : 1;
__REG32 :29;
} __usbdmaintst_bits;
/* CAN acceptance filter mode register */
typedef struct {
__REG32 ACCOFF :1;
__REG32 ACCBP :1;
__REG32 EFCAN :1;
__REG32 :29;
} __afmr_bits;
/* Global FullCANInterrupt Enable register */
typedef struct {
__REG32 FCANIE :1;
__REG32 :31;
} __fcanie_bits;
/* FullCAN Interrupt and Capture registers 0 */
typedef struct {
__REG32 INTPND0 :1;
__REG32 INTPND1 :1;
__REG32 INTPND2 :1;
__REG32 INTPND3 :1;
__REG32 INTPND4 :1;
__REG32 INTPND5 :1;
__REG32 INTPND6 :1;
__REG32 INTPND7 :1;
__REG32 INTPND8 :1;
__REG32 INTPND9 :1;
__REG32 INTPND10 :1;
__REG32 INTPND11 :1;
__REG32 INTPND12 :1;
__REG32 INTPND13 :1;
__REG32 INTPND14 :1;
__REG32 INTPND15 :1;
__REG32 INTPND16 :1;
__REG32 INTPND17 :1;
__REG32 INTPND18 :1;
__REG32 INTPND19 :1;
__REG32 INTPND20 :1;
__REG32 INTPND21 :1;
__REG32 INTPND22 :1;
__REG32 INTPND23 :1;
__REG32 INTPND24 :1;
__REG32 INTPND25 :1;
__REG32 INTPND26 :1;
__REG32 INTPND27 :1;
__REG32 INTPND28 :1;
__REG32 INTPND29 :1;
__REG32 INTPND30 :1;
__REG32 INTPND31 :1;
} __fcanic0_bits;
/* FullCAN Interrupt and Capture registers 1 */
typedef struct {
__REG32 INTPND32 :1;
__REG32 INTPND33 :1;
__REG32 INTPND34 :1;
__REG32 INTPND35 :1;
__REG32 INTPND36 :1;
__REG32 INTPND37 :1;
__REG32 INTPND38 :1;
__REG32 INTPND39 :1;
__REG32 INTPND40 :1;
__REG32 INTPND41 :1;
__REG32 INTPND42 :1;
__REG32 INTPND43 :1;
__REG32 INTPND44 :1;
__REG32 INTPND45 :1;
__REG32 INTPND46 :1;
__REG32 INTPND47 :1;
__REG32 INTPND48 :1;
__REG32 INTPND49 :1;
__REG32 INTPND50 :1;
__REG32 INTPND51 :1;
__REG32 INTPND52 :1;
__REG32 INTPND53 :1;
__REG32 INTPND54 :1;
__REG32 INTPND55 :1;
__REG32 INTPND56 :1;
__REG32 INTPND57 :1;
__REG32 INTPND58 :1;
__REG32 INTPND59 :1;
__REG32 INTPND60 :1;
__REG32 INTPND61 :1;
__REG32 INTPND62 :1;
__REG32 INTPND63 :1;
} __fcanic1_bits;
/* CAN central transmit status register */
typedef struct {
__REG32 TS1 : 1;
__REG32 TS2 : 1;
__REG32 : 6;
__REG32 TBS1 : 1;
__REG32 TBS2 : 1;
__REG32 : 6;
__REG32 TCS1 : 1;
__REG32 TCS2 : 1;
__REG32 :14;
} __cantxsr_bits;
/* CAN central receive status register */
typedef struct {
__REG32 RS1 : 1;
__REG32 RS2 : 1;
__REG32 : 6;
__REG32 RBS1 : 1;
__REG32 RBS2 : 1;
__REG32 : 6;
__REG32 DOS1 : 1;
__REG32 DOS2 : 1;
__REG32 :14;
} __canrxsr_bits;
/* CAN miscellaneous status register */
typedef struct {
__REG32 ES1 : 1;
__REG32 ES2 : 1;
__REG32 : 6;
__REG32 BS1 : 1;
__REG32 BS2 : 1;
__REG32 :22;
} __canmsr_bits;
/* CAN mode register */
typedef struct {
__REG32 RM :1;
__REG32 LOM :1;
__REG32 STM :1;
__REG32 TPM :1;
__REG32 SM :1;
__REG32 RPM :1;
__REG32 :1;
__REG32 TM :1;
__REG32 :24;
} __canmod_bits;
/* CAN command register */
typedef struct {
__REG32 TR :1;
__REG32 AT :1;
__REG32 RRB :1;
__REG32 CDO :1;
__REG32 SRR :1;
__REG32 STB1 :1;
__REG32 STB2 :1;
__REG32 STB3 :1;
__REG32 :24;
} __cancmr_bits;
/* CAN global status register */
typedef struct {
__REG32 RBS :1;
__REG32 DOS :1;
__REG32 TBS :1;
__REG32 TCS :1;
__REG32 RS :1;
__REG32 TS :1;
__REG32 ES :1;
__REG32 BS :1;
__REG32 :8;
__REG32 RXERR :8;
__REG32 TXERR :8;
} __cangsr_bits;
/* CAN interrupt capture register */
typedef struct {
__REG32 RI :1;
__REG32 TI1 :1;
__REG32 EI :1;
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