crc16generator_d8.vhd

来自「实现了SD的SPI模式,通过了所有的仿真及测试,支持数据的读和写.对SD卡的SP」· VHDL 代码 · 共 38 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.PCK_CRC16_D8.all;

entity CRC16Generator_D8 is
	port(
		TestData:in std_logic_vector(7 downto 0);
		Clock:in std_logic;
		Rst:in std_logic;
		Hold:in std_logic;
		CRC:out std_logic_vector(15 downto 0)
	);
end entity;

architecture behave of CRC16Generator_D8 is
signal next_crc:std_logic_vector(15 downto 0);
signal current_crc:std_logic_vector(15 downto 0);
begin
	process(current_crc,Hold,TestData)
	begin
		if Hold='0' then
			next_crc<=nextCRC16_D8(TestData,current_crc);
		else
			next_crc<=current_crc;
		end if;
	end process;
	
	process(Rst,Clock)
	begin
		if Rst='1' then
			current_crc<=(others=>'0');
		elsif Clock='1' and Clock'event then
			current_crc<=next_crc;
		end if;
	end process;
	CRC<=current_crc;
end architecture;