📄 pck_crc7_d1.vhd
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------------------------------------------------------------------------- File: PCK_CRC7_D1.vhd -- Date: Thu May 22 06:55:50 2008 -- -- Copyright (C) 1999-2003 Easics NV. -- This source file may be used and distributed without restriction -- provided that this copyright statement is not removed from the file -- and that any derivative work contains the original copyright notice-- and the associated disclaimer.---- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.---- Purpose: VHDL package containing a synthesizable CRC function-- * polynomial: (0 3 7)-- * data width: 1-- -- Info: tools@easics.be-- http://www.easics.com -----------------------------------------------------------------------library IEEE;use IEEE.std_logic_1164.all;package PCK_CRC7_D1 is -- polynomial: (0 3 7) -- data width: 1 function nextCRC7_D1 ( Data: std_logic; CRC: std_logic_vector(6 downto 0) ) return std_logic_vector;end PCK_CRC7_D1;library IEEE;use IEEE.std_logic_1164.all;package body PCK_CRC7_D1 is -- polynomial: (0 3 7) -- data width: 1 function nextCRC7_D1 ( Data: std_logic; CRC: std_logic_vector(6 downto 0) ) return std_logic_vector is variable D: std_logic_vector(0 downto 0); variable C: std_logic_vector(6 downto 0); variable NewCRC: std_logic_vector(6 downto 0); begin D(0) := Data; C := CRC; NewCRC(0) := D(0) xor C(6); NewCRC(1) := C(0); NewCRC(2) := C(1); NewCRC(3) := D(0) xor C(2) xor C(6); NewCRC(4) := C(3); NewCRC(5) := C(4); NewCRC(6) := C(5); return NewCRC; end nextCRC7_D1;end PCK_CRC7_D1;
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